Functional Description
3-9
DIs and ETIs must be armed and enabled for an interrupt to occur. Each interrupt can be
armed/disarmed and enabled/disabled individually. After power up initialization, all
interrupts are disarmed and disabled.
When the interrupt is armed, interrupt requests set a request bit. When an interrupt is
disarmed, any outstanding requests are turned off and ignored.
Requests for an enabled interrupt are allowed to enter the interrupt priority resolution
logic. The enable bit may be thought of as granting the RCIM board permission to deliver
any interrupt requests that it accepts. When the ETI or DI is disabled, it accepts interrupt
requests, but delays delivering the interrupt until it is re-enabled.
On RCIM III and RCIM II, the input to the interrupt block is used to drive the DI. On
RCIM I, the pending bit is the output of the ETI or DI. This output is routed to the host
computer to which the RCIM board is attached, and additionally to other systems in the
RCIM chain if configured to do so. The ETI or DI interrupt handler on the host clears the
pending bit each time it concludes the processing of an interrupt. This clears the way for
the RCIM board to output the next instance of this interrupt.
Arming and Enabling DIs and ETIs
1
DIs and ETIs are armed using the
ioctl(2)
system call with the following operations,
which can be used interchangeably:
DISTRIB_INTR_ARM
ETI_ARM
DIs and ETIs are enabled using
ioctl(2)
with the following operations, which can be
used interchangeably:
DISTRIB_INTR_ENABLE
ETI_ENABLE
Interrupt Recognition Logic
1
By default, the RCIM looks for the leading edge of an input signal to trigger an interrupt.
Once the interrupt is recognized, it must be deasserted and reasserted to cause a new
interrupt request. Optionally, an interrupt may be configured as level-sensitive. In this
mode, an interrupt is triggered when the interrupt signal is high or low. Configuration
options are included with the documentation for each type of interrupt later in this chapter.
For the RCIM to be able to reliably extract interrupts from an input signal, the equipment
generating the signal must hold any value generated for at least 1.5 microseconds before
transitioning to the reset value.
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