CommTech FASTCOM SuperFASTCOM Hardware Reference Manual Download

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CONTENTS

“CE” CERTIFICATE

.............................................................................................................. 1

INTRODUCTION

Description / Block Diagram

............................................................................................ 3

Specifications / Features

................................................................................................. 4

Board Layout

................................................................................................................... 5

Communications Overview

.............................................................................................. 6

Comparison to ESCC Family

........................................................................................... 8

CABLE

Cable Configuration

......................................................................................................... 9

DB25 Connector Description

......................................................................................... 10

INSTALLATION

Hardware Installation

..................................................................................................... 11

Software Installation

...................................................................................................... 11

TESTING THE INSTALLATION

Windows 2000 Test Procedure

...................................................................................... 11

SOFTWARE UTILITIES

...................................................................................................... 12

PROGRAMMING

................................................................................................................ 14

MEMORY MANAGEMENT

................................................................................................. 16

RS-422/485

......................................................................................................................... 17

Termination Resistance

................................................................................................. 18

PROGRAMMABLE CLOCK GENERATORS

...................................................................... 19

ERRATTA

........................................................................................................................... 20

TECHNICAL SUPPORT

..................................................................................................... 23

APPENDIX

Infineon 20534 Technical Data Sheet

............................................................................ 24

Summary of Contents for FASTCOM SuperFASTCOM

Page 1: ...erutilized and idle equipment along with credit for buybacks and trade ins Custom engineering so your equipment works exactly as you specify Critical and expedited services Leasing Rentals Demos In stock Ready to ship TAR certified secure asset solutions Expert team I Trust guarantee I 100 satisfaction All trademarks brand names and brands appearing herein are the property of their respective owne...

Page 2: ...F A ASTCOM DAPTERS SuperFASTCOM Four Channel High Speed Synchronous Serial Adapter for PCI Bus Hardware Reference Manual Manufactured by 9011 E 37th St N Wichita KS 67226 2006 ...

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Page 4: ...T C 2001 2002 2003 2004 2005 All rights reserved including those to reproduce this document or parts thereof in any form without permission in writing from Commtech Inc FASTCOM is a trademark of Commtech Inc Microsoft is a registered trademark of Microsoft Corporation WINDOWS is a trademark of Microsoft Corporation ...

Page 5: ... Removed RS 530 references 2 7 1 13 Changed board revision level on CE certificate Removed unnecessary register setup information and repaginated 2 8 1 Added SuperFastcom family information 2 9 18 Changed warranty period to lifetime 2 10 12 13 Added more programs to list 2 11 19 21 Added Errata section Modified features to agree with errata 2 12 21 Appended to Errata section 2 13 11 Add hardware i...

Page 6: ...onfiguration 9 DB25 Connector Description 10 INSTALLATION Hardware Installation 11 Software Installation 11 TESTING THE INSTALLATION Windows 2000 Test Procedure 11 SOFTWARE UTILITIES 12 PROGRAMMING 14 MEMORY MANAGEMENT 16 RS 422 485 17 Termination Resistance 18 PROGRAMMABLE CLOCK GENERATORS 19 ERRATTA 20 TECHNICAL SUPPORT 23 APPENDIX A Infineon 20534 Technical Data Sheet 24 ...

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Page 8: ...s B Limits EN 50082 1 1992 EMC Generic Immunity Standard Part 1 Residential Commercial and Light Industry IEC 801 2 1984 Method of Evaluating Susceptibility to Electrostatic Discharge Level 4 IEC 801 3 1984 Radiated Electromagnetic field Requirements Level 3 IEC 801 4 1988 Electrical Fast Transient Burst Requirements Level 2 Products listed on this declaration are exempt from the requirements of t...

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Page 10: ...external clock The board also features high speed RS 422 RS 485 drivers receivers with on board line termination Programming is simplified with the inclusion of drivers example programs and comprehensive documentation supplied on the Fastcom CD The SuperFASTCOM provides high speed and high reliability while greatly reducing development time and system complexity The SuperFASTCOM family includes Fo...

Page 11: ...ION DB 78 to four DB 25 connectors BUS INTERFACE 32 bit PCI Ver 2 1 POWER REQUIREMENTS 450mA 5 typical ENVIRONMENT Operating Temperature Range 0 to 70 C Humidity 0 to 90 non condensing MEAN TIME BETWEEN FAILURES 24 61 Yrs CERTIFICATION FCC compliant CE marked FEATURES Four independent channels Status LEDs for system development debugging Two programmable on board clock generators Switchless design...

Page 12: ...BOARD LAYOUT Commtech Inc Wichta KS DB78 CONNECTOR TRANSMIT RECEIVE STATUS LEDs PACKING LIST SuperFASTCOM Card SuperFASTCOM Cable FASTCOM CD If an omission has been made please call technical support for a replacement ...

Page 13: ... 7D H for mapped characters Asynchronous ASYNC Protocol Mode Selectable character length 5 to 8 bits Even odd forced or no parity generation checking 1 or 2 stop bits Break detection generation In band flow control by XON XOFF Immediate character insertion Termination character detection for end of block identification Time out detection Error detection parity error framing error BISYNC Protocol M...

Page 14: ...he buffer size is 128 32 bit words each Programmable buffer size in transmit direction per channel buffer allocation in receive direction on request Programmable watermark for receive channels to control transfer of receive data to host memory Two programmable watermarks for each transmit channel i e one controlling data loading from host memory and one controlling transfer of transmit data to the...

Page 15: ...maskable Enhanced time slot assigner Support of high data rates 45 Mbit s for DS3 or 52 Mbit s for OC1 Protocol support is limited to HDLC Sub modes without address recognition Simplifications of the ESCC Serial Core The following features of the ESCC core have been removed SDLC Loop mode Extended transparent mode 0 this mode provided octet buffered data reception without usage of FIFOs the SuperF...

Page 16: ...NEL 1 CHANNEL 2 CHANNEL 3 CHANNEL 4 GND 1 58 38 9 48 GND 7 68 29 10 49 SD 2 70 13 22 62 SD 14 50 32 2 46 RD 3 73 36 6 65 RD 16 53 17 26 42 RTS 4 71 33 3 63 RTS 19 51 14 23 45 CTS 5 74 18 27 66 CTS 13 54 37 7 41 DCD 10 76 31 8 40 DCD 8 57 12 28 60 TT 11 69 30 1 61 TT 24 52 11 21 47 RT 9 72 16 25 64 RT 17 56 35 5 43 ST 12 75 34 4 67 ST 15 55 15 24 44 PRGCLK 23 77 N A N A N A PRGCLK 20 78 N A N A N A...

Page 17: ...A SD 14 TRANSMIT DATA B SD 3 RECEIVE DATA A RD 16 RECEIVE DATA B RD 4 REQUEST TO SEND A RTS 19 REQUEST TO SEND B RTS 5 CLEAR TO SEND A CTS 13 CLEAR TO SEND B CTS CLOCK SIGNALS PIN DESCRIPTION 422 TYPE CONNECTED TO 8 DATA CARRIER DETECT A DCD 10 DATA CARRIER DETECT B DCD 24 TRANSMIT CLOCK OUT A TT 11 TRANSMIT CLOCK OUT B TT 17 RECEIVE CLOCK IN A RT 9 RECEIVE CLOCK IN B RT 15 TRANSMIT CLOCK IN A ST ...

Page 18: ... the blank bracket from your PC install the SuperFASTCOM in the PC by pressing it firmly into the slot Install the bracket screw to hold it firmly in place 4 Re install the cover on your PC 5 Install the SuperFASTCOM cable Software Installation Select the link above to open the Installation Manual Under SuperFastcom select your operating system and follow the instructions When you are finished sel...

Page 19: ... CD or downloaded from our website at http www commtech fastcom com They are meant to be used as educational tools and programming references when designing your own software sfcset exe Use to change register settings in conjunction with the hdlcset file hdlcset asyncset bisyncset Generic settings files to be used with sfcset exe getclock exe returns programmable clock 1 rate osc getclock2 exe ret...

Page 20: ...ings getclock2 exe user program to get the current program clock generator settings read_file_hdlc exe user program to read hdlc frames from a port and stuff them to a file sendfile exe user program to send a file out a SuperFastcom port setchecktimeout exe user mode function to set the timeout timer in the driver that checks for frames to be returned or sent setfs6131clock exe user program that s...

Page 21: ...ve constantly enabled Bit 4 0 receive enabled only when RTS is off 1 transmit constantly enabled Bit 5 0 transmit enabled only when RTS is on 1 TT constantly enabled Bit 6 0 TT enabled only when RTS is on Bit 7 No function Register at offset 2 Channel 1 Channel 3 0 ST connected to TXCLK 0 ST connected to TXCLK Bit 0 1 ST not connected Bit 4 1 ST not connected 0 TT connected to TXCLK 0 TT connected...

Page 22: ...e driver If that pin is configured to be an input then it must be connected to a line receiver The ST pin is TxClk as an input and the TT pin is TxClk as an output ST connected to TxClk TxClk connected to the ST input pin Never set CCR0 TOE 1 when setting this bit ST not connected to TxClk default TxClk not connected to the ST input pin TT connected to TxClk default TxClk connected to the TT outpu...

Page 23: ...erefore there is no reduction in processor performance due to data communication overhead How it works The user designates in his program how much system memory will be allocated to communications the more memory in your system the more you can allocate to the communication process As data is received the on board communication processor fills a small local buffer When this is full the bus master ...

Page 24: ...ceive signal RX in RS 232 consists of RD and RD Another draw back of RS 232 is that more than two devices cannot share a single cable This is also true of RS 422 and that s why the RS 485 standard was developed RS 485 offers all of the benefits of RS 422 and also allows multiple units up to 32 to share the same twisted pair RS 485 is often referred to as a multi drop or two wire half duplex networ...

Page 25: ...e is built in We have installed a terminator resistor for each receiver between each RD and RD and between CTS and CTS for each channel If you are using the SuperFastcom in a multi drop network the termination resistor should be removed from all units except the first and last see the RS 485 illustration below Call for technical support if you need to modify the resistor You may also order the Sup...

Page 26: ...GPP register bits 10 and 11 The PROGCLK is designed to provide a system wide high speed clock pulse For additional information on the Cypress ICD2053B please review the data sheet An important fact about the clock generator There is only one clock input line on the PEB 20534 communications chip and it is connected to the OSC clock generator on the SuperFastcom board The OSC clock generator can be ...

Page 27: ...t frame is in the range of 1 5 2 The receive CRC checking mode is selected to transfer the receive CRC into the receive FIFO CCR2 RCRC 1 In all cases meeting the first condition the number of 1 bits is treated as an invalid HDLC frame This frame is prevented from being reported or forwarded to the receive FIFO because of its invalid length However the serial receive logic calculates a receive stat...

Page 28: ...n of a frame sometimes resulting in endless repetition of a byte or in failure of the responding S frame Then this channel does not respond autonomously to further reception events Workaround None Do not use full duplex Automode Command Execution CEC Status Bit Error With External Clocking In general the PEB20534 supports external clock gapping in any clock mode in which the internal transmit or r...

Page 29: ...ther this is a bug in the PEB20534 or whether it was done by design but the port that will be receiving in Ext Trans Mode must be initialized in clock mode 1 with a clock present on the RT pins It can then be switched to any other clock mode and will operate correctly Workaround If your configuration already uses an external receive clock simply initialize the card in clock mode 1 CCR0 CM2 CM0 001...

Page 30: ...tch positions your cables and your program We recommend that you build the loop back plug that is described in the Programming section of this manual With that plug you can quickly isolate the problem to the board cables or software If you still have unresolved questions use the following procedure to get technical support 1 Call our Technical Support Staff at 316 636 1131 They are on duty from 9 ...

Page 31: ...24 APPENDIX A INFINEON 20534 TECHNICAL DATA ...

Page 32: ...quipment Have surplus equipment taking up shelf space We ll give it a new home Learn more Visit us at artisantg com for more info on price quotes drivers technical specifications manuals and documentation Artisan Scientific Corporation dba Artisan Technology Group is not an affiliate representative or authorized distributor for any manufacturer listed herein We re here to make your life easier How...

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