CommTech FASTCOM SuperFASTCOM, Hardware Reference Manual, Page: 26 / 32

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PROGRAMMABLE CLOCK GENERATORS
The SuperFastcom features two Programmable Clock Generators. Each is a Cypress
ICD2053B chip, which offers a fully user-programmable phase-locked loop clock pulse
generator in a single 8-pin package. The output of the generator may be changed "on the fly"
to any desired frequency value. The ability to dynamically change the output frequency adds a
whole new degree of freedom for the designer.
Why have two clock generators?
The first clock generator (the
OSC clock generator) provides the clock pulse to the PEB20534
communications processor chip. Its maximum frequency is 33MHz and is programmable via
the GPP register (bits 8 and 9). The second clock generator (the
PROGCLK clock generator)
directly drives the and PROGCLK- output signals (PIN 20 and 23 on Cable #1).
The PROGCLK has a maximum frequency of 40MHz and is programmable via the GPP
register (bits 10 and 11). The PROGCLK is designed to provide a system wide high-speed
clock pulse.
For additional information on the Cypress ICD2053B, please review the
data sheet .
An important fact about the clock generator
There is only one clock input line on the PEB 20534 communications chip and it is connected
to the
OSC clock generator on the SuperFastcom board. The OSC clock generator can be
programmed from any channel (SFC, SFC1, SFC2, SFC3) but you are programming the same
clock generator (the OSC clock generator) in each case. Just keep in mind that the baud rate
generators are independent for each channel, but all four baud rate generators are fed from
one clock source (the OSC clock generator). If you change the OSC clock generator rate you
will change the input to the baud rate generators for all channels.
If you have multiple baud rates that must be generated on multiple channels, you should select an OSC
clock rate from which all of the required baud rates can be derived.
Changing the OSC clock generator
output will affect the baud rates of all channels!!!!