CommTech FASTCOM ESCC-PCI-335, Hardware Reference Manual

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The input clock will depend on the clock mode. It is usually either the OSC input or the RXCLK (RT+/-) input (see
table 5 page 84 of the 82532 data sheet).
If BDF = 1 BGR = 1
If BDF = 0 BGR = (N+1)*2
If BDF = 0 and EBRG = 1 BGR = (n+1)*2^m (V 3.x of the 82532 silicon only)
The BDF bit is in CCR2 (bit 5)
N = (CCR2&0xC0)<<2) + BGR, or if you prefer
Most significant ......................................................................... Least significant bit
m = CCR2 bit 8,CCR2 bit 7, BGR bit 7, BGR bit 6
n = BGR 5, BGR 4, BGR 3, BGR 2, BGR 1, BGR 0
N = CCR2 8,CCR2 7, BGR 7, BGR 6, BGR 5, BGR 4, BGR 3, BGR 2, BGR 1, BGR 0
If you are using the DPLL, you should try to set its input clock to be as close to the actual bit frequency as
possible. This will allow for optimal clock recovery. Also, clock recovery relies on edges in the data stream; if you
transmit long segments of 0s or 1s using an encoding method that produces no edges, the results will be non-
optimal. The ideal encoding for clock recovery is Manchester or a non ‘1’ idle pattern (i.e., constant flag
sequences on idle if HDLC is used, etc.).
Let’s start with something easy
Let’s say that you want to set up an ESCC channel to run in HDLC mode at 19200 bps, that the device in
question supplies a clock with its data (receive clock), and that we need to generate (transmit) a clock that
matches our transmitted data. To achieve this we should set the 82532 to clock mode 0b. Set the mode switch
position 5 (or 7) to on, enabling the txclk output driver (selecting txclk as an output on TT+/-). The baudrate
function bitrate = input clock / (N+1)*2 will be used. If there are no other constraints other than operating one
channel at 19200 bps, then we can select both the input clock and N arbitrarily, so long as we do not violate any
of the notes.
So, by selecting a value for input clock that is less than 10 MHz (since the bit rate is slow we will want to use
master clock mode, which will require a 10 MHz or less clock), we can then calculate the value needed for N to
get a 19200 bps output. I will pick 7.372800 MHz for the input clock. To set this frequency, run:
setclock.exe 0 7372800
Calling the IOCTL_ESCCDRV_SET_CLOCK_FREQ ioctl function with 7372800 as the desired frequency will also
get us an input clock of 7.3728 MHz (referred to as OSC in table 5).
Then solving for N we get:
19200 = 7.3728E6/((N+1)*2)
N = 191 = 0x0BF
Checking the notes to make sure we did not violate anything:
Fm/Fx = 7.3728E6/19200 = 384 > 2.5 (we are OK on this one)
Fr/Fm = rxclk input / 7.3728E6 < 3 (assuming a 19200 clock input) 19200/7.3728E6 = .0026 < 3 (we are
OK on this one)
(0x0BF & 0x3f) <= 0 (checking the value of n to make sure it isn’t forced to zero due to the glitch in the
82532)