BAT32G1x9 user manual | Chapter 10 Timer M
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10.7 Considerations when using timer M
10.7.1
Read and write access to SFR
To set the timer M, you must first place the TMMEN position of the PER1 register "1". When the TMMEN bit is
"0", the write operation of the control register of timer M is ignored, and the read values are initial values (except
for port registers and port mode registers).
The following registers are prohibited during the counting process:
TMELC registers, TMMR registers, TMPMR registers, TMFCR registers, TMOER1 registers,
TMPTO bits, TMDFi registers, TMCRi registers, TMIORAi registers, TMOERAi registers, TMOER2
registers, TMOER2 registers, TMDFi registers, TMD, TM, TMD, TMD, T
TMIORCi registers, TMPOCRi registers
(1) TMSTR registers
• Ability to set TMSTR registers via 8-bit memory manipulation instructions.
• When the CSELi bits of the TMSTR register (i=0, 1) are "0" (in the TMi register and TMGRAi register
comparison stop count when matching), even if you write "0" (stop count) to the TSTARTi bit, the stop
count is not stopped and the TSTARTi bit does not change. The TSTARTi bit becomes "0" (stop count)
only when it matches the TMGRAi register.
When rewriting the TMSTR register, if you want to change the CSELi bit to "1" without affecting the count
with the CSELi bit being "0", you must give it to TSTARTi Bit writes "0".
If you write "1" to the TSTARTi bit while the counter stops counting, you may start counting. To stop
counting programmatically, you must write "0" to the TSTARTi bit after the CSELi position "1". Even if
you write "1" and "0" to the CSELi bit and the TSTARTi bit at the same time (using 1 instruction), the
count cannot be stopped.
• The output level during the count stop when
the TMIOji pin (j=A, B, C, D) is used for the timer M output
as shown in Table 10-19 as shown.
The output levels of
the TMIOji pins (j=A, B, C, D) when Table 10-19 stop counts
The method that stops counting
Stop counting the output level of the TMIOji pin
When the CSELi bit is "1", stop counting by writing "0" to
the TSTARTi bit.
Maintain the output level before stopping counting (in
complementary PWM mode of timer M or reset
synchronous PWM mode, the initial output level of the
OLS0 bit of the output TMFCR register and the OLS1 bit of
the output TMFCR register are selected).
When the CSELi bit is "0", the count stops when the TMi
registers and the TMGRAi registers are relatively
matched.
Keep the comparison matching level after the output
change is caused (in the complementary PWM mode of
timer M or the reset synchronous PWM mode, the initial
output level of the OLS0 bit of the output TMFCR register
and the OLS1 bit of the output is selected).
Remark
i=0, 1,j=A, B, C, D
(2) TMDFi registers (i=0, 1).
Counting must begin after setting the DFCK0 and DFCK1 bits of the TMDFi register.
(3) TMi registers (i=0, 1).
If the value of the TMi register changes to "0000H" and the timing of the write TMi register overlaps, the
register is preferred.
10.7.2
Switching modes
•
To switch modes during operation, it must be switched after entering the count stop state
(TSTART0 bit and TSTART1 position "0").
•
Before changing the TSTART0 bit and TSTART1 bit from "0" to "1", the TMIF0 bit and TIF1 bits
must be in the
position “0”
。
For details, please refer to "Chapter 25 Interrupt Function".
