V.22 bis Modem with AT Commands
CMX866
©
2008 CML Microsystems Plc
36
D/866/5
equaliser) that will automatically compensate for a wide range of line conditions in both QAM and DPSK
modes. It must be enabled when receiving 2400bps QAM by setting bit 2 of the S24 register. The auto-
equaliser can provide a useful improvement in performance in 1200bps DPSK as well as 2400bps QAM
modes, so although it must be disabled at the start of a handshake sequence, it can be enabled as soon
as scrambled 1200bps 1s have been detected.
Both FSK and QAM/DPSK demodulators produce a serial data bit stream which is fed to the Rx pattern
detector, descrambler and USART block (see Figure 9a). In QAM/DPSK modes the demodulator input is
also monitored for the V.22 bis handshake ‘S1’ signal.
The QAM/DPSK demodulator also estimates the received bit error rate by comparing the actual received
signal against an ideal waveform. This estimate is placed in bits 2-0 of the DSP Status Register.
However, the estimate is not required for CMX866 operation and so is ignored by the on-chip µController.
1.5.12 Rx Modem Pattern Detectors and Descrambler
See Figure 9a.
The 1010.. pattern detector operates only in FSK modes and will set bit 9 of the DSP Status Register
when 32 bits of alternating 1’s and 0’s have been received.
The ‘Continuous Unscrambled 1’s’ detector operates in all modem modes and will set bits 8 and 7 of the
DSP Status Register to 01 when 32 consecutive 1’s have been received.
The descrambler operates only in DPSK/QAM modes and is enabled automatically by the on-chip
µController.
The ‘Continuous Scrambled 1’s’ detector operates only in DPSK/QAM modes when the descrambler is
enabled and will set bits 8 and 7 of the DSP Status Register to 11 when 32 consecutive 1’s appear at the
output of the descrambler. To avoid possible ambiguity, the ‘Scrambled 1’s’ detector is disabled when
continuous unscrambled 1’s are detected.
The ‘Continuous 0’s’ detector will set bits 8 and 7 of the DSP Status Register to 10 when NX consecutive
0’s have been received, NX being 32 except when DPSK/QAM Start-Stop mode has been selected, in
which case NX = 2N + 4 where N is the number of bits per character including the Start, Stop and any
Parity bits.
All of these pattern detectors will hold the ‘detect’ output for 12 bit times after the end of the detected
pattern unless the received bit rate or operating mode is changed, in which case the detectors are reset
within 2ms.
The DSP Status Register is automatically polled by the on-chip µController, which then interprets the
results of these pattern detectors.
1.5.13 Rx Data Register and USART
A flexible Rx USART is provided for all modem modes. It can be programmed by bits 6 and 7 of the S26
register to treat the received data bit stream as Synchronous data or as Start-Stop characters.
In Synchronous mode the received data bits are all sent to the Rx Data Buffer, which is copied into the
DSP Rx Data Register after every 8 bits.
In Start-Stop mode the USART Control logic looks for the start of each character, then sends only the
required number of data bits (not parity) to the Rx Data Buffer. The parity bit (if used) and the presence of
a Stop bit are then checked and the data bits in the Rx Data Buffer copied into the DSP Rx Data Register.