Schematic Diagrams
B - 4 Processor 2/7- CLK, MISC
B.Schematic Diagrams
Processor 2/7- CLK, MISC
H _P R OC H O T #
H _ C P U P W R GD _ R
1 . 5 V
6 , 9 , 10 , 2 5 , 2 9, 3 3 , 3 5, 37 , 3 8
H _ P E C I
2 3, 3 4
H _ P M_ S Y N C
2 0
C AD No te : Ca pac it or
n eed t o be p lac ed
c los e to b uf fer
o utp ut p in
3 . 3V _E N _ D
1. 5 V S _ C P U _ P W R GD
TRACE WIDTH 10MIL, LENGTH <500MILS
H _ C P U P W R GD _ R
Processor Pull downs
R 5 7 2
*1 0 K _0 4
B U F _ C P U _ R S T #
12/1
Add
PU/PD for JTAG signals
1 . 0 5 V S _ V TT
2 , 5, 2 3 , 2 4, 25 , 3 5 , 37 , 3 9
C L K _ B C LK
1 9
1. 5 V S _ C P U
6 , 35
3 . 3 V
2 , 8, 1 1 , 1 6, 18 , 1 9 , 20 , 2 2 , 2 3, 2 4 , 2 5, 2 7 , 2 8 , 29 , 3 0 , 3 5, 3 7 , 3 8, 3 9
C L K _ D P
1 9
C L K _ D P #
1 9
C L K _ B C LK #
1 9
D R A MR S T _ C N T R L
8 , 19
3 . 3 V S
9 , 10 , 1 1 , 12 , 1 8 , 1 9, 2 0 , 2 1, 22 , 2 3 , 24 , 2 5 , 2 7, 2 8 , 3 0, 31 , 3 2 , 33 , 3 4 , 3 5, 3 9
H _ C P U P W R GD
23
H _ P R OC H OT # _ E C
3 4
XD P _ D B R _R
H _P R OC H O T #
3 9
S M_ R C OM P _ 2
S M_ R C OM P _ 1
S M_ R C OM P _ 0
XD P _ TR S T #
XD P _ TC L K
V D D P W R GO OD _R
H _ P R OC H O T# _ R
XD P _ TM S
C P U _D R A M R S T #
XD P _ P R E Q #
XD P _ TD I _ R
XD P _ TD O_ R
R 4 0 1
*1 0 mi l _ sh o rt _ 04
R 1 4 8
*3 9 _0 4
R 22 2
*0 _ 04
R 4 4 1
75 _ 0 4
C 1 35
47 p _ 50 V _ N P O _ 04
R 4 40
1 0 0 K _0 4
R 2 20
1 K _ 0 4
R 8 8
6 2 _ 04
R 4 0 3
1 K _ 0 4
R 4 0 0
*1 0 mi l _ sh o rt _ 04
Q1 3
*MT N 70 0 2 Z H S 3
G
D
S
R 8 2
*1 0 mi l _ sh o rt _ 04
S
D
G
Q3 1 B
L 2 N 7 00 2 D W 1T 1 G
5
3
4
R 3 9 9
1 0 K _ 04
R 4 3 9
43 _ 1 %_ 0 4
R 1 4 7
*2
0
0
_0
4
S
D
G
Q3 1 A
L 2N 7 00 2 D W 1T 1 G
2
6
1
R 1 56
* 1 0K _ 0 4
CL
O
CKS
MI
SC
TH
ER
MA
L
P
WR
MA
N
AGE
ME
NT
DD
R3
MI
SC
JT
AG
&
BP
M
U 2 9B
P Z 98 8 2 7- 3 6 4 B -0 1F
S M _R C O MP [ 1 ]
A 5
S M _R C O MP [ 2 ]
A 4
S M _ D R A MR S T#
R 8
S M _R C O MP [ 0 ]
A K 1
B C L K #
A 2 7
B C L K
A 2 8
D P L L _R E F _ S S C L K #
A 1 5
D P L L_ R E F _ S S C L K
A 1 6
C A TE R R #
A L3 3
P E C I
A N 3 3
P R OC H O T#
A L3 2
T H E R MT R I P #
A N 3 2
S M _D R A MP W R OK
V 8
R E S E T #
A R 3 3
P R D Y #
A P 29
P R E Q#
A P 27
T C K
A R 2 6
T MS
A R 2 7
T R S T#
A P 30
T D I
A R 2 8
T D O
A P 26
D B R #
A L 3 5
B P M# [ 0 ]
A T 2 8
B P M# [ 1 ]
A R 2 9
B P M# [ 2 ]
A R 3 0
B P M# [ 3 ]
A T 3 0
B P M# [ 4 ]
A P 32
B P M# [ 5 ]
A R 3 1
B P M# [ 6 ]
A T 3 1
B P M# [ 7 ]
A R 3 2
P M _S Y N C
A M3 4
S K T O C C #
A N 3 4
P R OC _S E LE C T #
C 2 6
U N C OR E P W R G OO D
A P 3 3
Q 1 0
M T N 7 0 02 Z H S 3
G
D
S
TRACE WIDTH 10MIL, LENGTH <500MILS
Processor Pull up
Q 1 6
* MT N 7 0 0 2Z H S 3
G
D
S
R 1 5 3
*1
00
K
_
0
4
R 9 1
5 6 _1 % _ 0 4
R 4 2 0
51 _ 0 4
R 4 4 3
20 0 _ 1% _ 0 4
R 4 0 2
*1 0 mi l _ sh o rt _ 04
R 4 1 4
51 _ 0 4
R 4 36
1 0 K _ 0 4
R 14 4
1 3 0_ 1 % _ 04
C 6 5 2
0 . 04 7 u _1 0 V _ X7 R _0 4
R 1 4 5
20 0 _ 1% _ 0 4
R 4 1 8
51 _ 0 4
R 4 4 6
14 0 _ 1% _ 0 4
R 2 1 7
1 K _ 0 4
Q2 0
MT N 7 0 0 2Z H S 3
G
D
S
R 4 1 6
51 _ 0 4
R 1 50
0 _0 4
C 2 4 8
*
0.
1
u
_
16
V
_
Y5
V_
04
R 4 4 2
25 . 5 _ 1% _ 0 4
R 4 1 5
*5 1 _0 4
H _ P M _S Y N C _ R
R 2 1 8
4 . 9 9K _1 % _ 04
R 15 7
* 10 K _ 0 4
U 1 0
* 7 4A H C 1 G 09
1
2
5
4
3
R 4 1 0
51 _ 0 4
R 9 4
1 0 0 K _0 4
If PR OC HO T# i s not u se d,
th en it m us t be te rm in at ed
wi th a 56 -O + -5 % p ul l- up
re sis to r to 1 .0 5VS _V TT .
DDR3 Compensation Signals
B U F _ C P U _ R S T #
S M_ R C OM P _ 1
S M_ R C OM P _ 0
S M_ R C OM P _ 2
3 . 3 V S
1. 05 V S _ V T T
D D R 3 _D R A M R S T #
9, 1 0
H _S N B _ I V B #
2 3
H _ TH R M T R I P #
2 3
XD P _ B P M0 _ R
XD P _ B P M1 _ R
XD P _ B P M2 _ R
XD P _ B P M4 _ R
XD P _ B P M3 _ R
XD P _ B P M5 _ R
XD P _ B P M6 _ R
XD P _ B P M7 _ R
XD P _ P R D Y #
P M S Y S _ P W R GD _ B U F
Q 17
* B S S 1 38 _ N L
G
D
S
P L T _ R S T #
1 2 , 22 , 2 8
P M_ D R A M _P W R GD
20
S U S B
3 5, 3 7 , 3 8
1. 5V S _C P U _ P W R GD
38
H _ T H R MT R I P #_ R
S3 circuit:- DRAM PWR GOOD logic
Sandy Bridge Processor 2/7 ( CLK,MISC,JTAG )
12/1
? ? ?
Buffered reset to CPU
3. 3 V S
1 . 5 V S _ C P U
3. 3 V
3 . 3 V
3 . 3V
1 . 5V S _C P U
1. 5 V
1 . 0 5V S _V T T
3 . 3 V S
1 . 0 5V S _V T T
H _ P E C I _ R
C P U _ D R A MR S T#
S3 circuit:- DRAM_RST# to memory
should be high during S3
X D P _ D B R _ R
H _ C A T E R R #
XD P _ TR S T #
H _ S N B _ I V B #
XD P _ TD O_ R
XD P _ TC L K
XD P _ TD I _ R
XD P _ TM S
XD P _ P R E Q #
P MS Y S _ P W R GD _B U F
Sheet 3 of 49
Processor 2/7-CLK,
MISC
Summary of Contents for W251HNQ
Page 1: ...W251HPQ W251HPQ C W251HNQ W251HNQ C W255HP W255HN W258HPQ W258HPQ C W258HNQ ...
Page 2: ......
Page 24: ...Introduction 1 12 1 Introduction ...
Page 44: ...A 4 Top W255HP W255HN A Part Lists Top W255HP W255HN 灰色 非耐落 Figure A 2 Top W255HP W255HN ...
Page 46: ...A 6 Bottom A Part Lists Bottom Figure A 4 Bottom ...
Page 47: ...SATA BLU RAY COMBO A 7 A Part Lists SATA BLU RAY COMBO 非耐落 志精 Figure A 5 SATA BLU RAY COMBO ...
Page 48: ...A 8 DVD DUAL A Part Lists DVD DUAL Figure A 6 DVD DUAL 非耐落 志精 ...
Page 49: ...LCD A 9 A Part Lists LCD 頭厚 非耐落 中性 Figure A 7 LCD ...
Page 50: ...A 10 A Part Lists ...
Page 103: ...www s manuals com ...