Clevo W150DAQ, Service Manual

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Schematic Diagrams
SB820M- STRAPS/POWERGD 5/5 B - 27
B.Sch
e
m
a
tic D
iag
rams
SB820M- STRAPS/POWERGD 5/5
Sheet 26 of 48
SB820M- STRAPS/
POWERGD 5/5
P C I _A D 2 8 22
P C I _A D 2 9 22
Up dated on Rev2.1
R 5 95 0 _0 4
C 5 52
*2 . 2u _1 6V _ X5 R _0 6
N B _ PW R G D 23
1 V1 D U A L_ P WR G D 3 9
N B _ PW R GD _ I N 7
R 3 56
1 0K _ 04
1. 2V _ P WR G D
3. 3 V S
S B _P W R G D 20 , 23
S Y S _R S T # 23
SU SB # 2 3, 3 2, 3 3, 36 , 38
1. 8V S
PW R G D _ V C OR E
R 3 57 0 _0 4
1V 8_ P WR G D
1V 1D U AL _P W R GD
D D R 1. 5 V _P W R GD
R 5 94
3 00 _1 %_ 04
D 2 1 R B 7 51 V
A C
D 3 5 *R B 7 51 V
A C
P W R GD _V C O R E 4 0, 4 1
D 1 8 R B 7 51 V
A C
D 1 6 R B 7 51 V
A C
D 3 6 R B 7 51 V
A C
D 2 0 R B 7 51 V
A C
D 1 9 R B 7 51 V
A C
1 .1 V S _N B _P W R GD 4 0
A Z _S D A T A_ OU T 23 ,2 9
1 V8 _P W R GD 3 9
Res istors mar ked with "A11 " is only for SB8 00A11 ONLY.
P E _G P I O 1 2 2
MX M_P W R _E N 2 2, 2 3
LD R Q#1 2 2
S B _P C I E _1 39 4_ C LK R E Q# 2 2
S D _O N 2 3
P X_ E N # 2 2
S E R I R Q 2 0, 2 2, 3 3
MX M_P W R GD 2 2, 4 2
S B _P C I E _L AN _C L KR EQ # 2 3
P C I _I N T G# 2 2
P E _GP I O0 1 2, 2 2
P E R R # 2 2
LO C K # 2 2
I R D Y # 2 2
S TOP # 2 2
P C I _GN T# 0 2 2
S B _GP I O _P C I E _ R ST # 2 2, 2 3
D E V S EL # 2 2
S B _P C I E _D T _C L K R E Q# 2 2
F R A ME # 2 2
S E R R # 2 2
P C I _C L K R U N # 2 0, 2 2
P C I _R E Q # 0 2 2
TR D Y # 2 2
S MA R TV OL T2 2 3
S B _P C I E _P E 2_ C LK R E Q# 2 3
S B _P C I E _U S B 30 _C L K R E Q# 2 2
S B _P C I E _E XP C A R D _ C L KR E Q # 2 3
D E FA U L T
USE DE FAULT
PCIE STRAPS
PULL
HIGH
E C
DISABLED
USE EEPROM
PCIE
STRAPS
GPIO200
Watchdo g
T im er
Enabled
USE PCI
PL L
PCI_CLK4
E C
E NABLED
PCI_AD24
D E FA U L T
PCI_CLK3
SB800 HAS 1 5K INTERNAL PU FOR PCI_AD[27:23]
PULL
LOW
D EF A U L T
USE FC
PLL
IGNORE
DE
BUG
STRAP
CLKGEN
DISABLED
D E F A U LT
D EF A U L T
DISABLE PCI
ME
M BOOT
D E FA U L T
PCI_AD25
D EF A U L T
CLKGEN
ENABLED
D E F AU LT
D E F A U LT
O VER LAP C OM M O N PADS WH ERE
PO SSIBL E F OR DU AL-O P
RESI STORS.
ENABLE ILA
AUTORUN
F USION
CLOCK
MODE
BYPASS FC
PLL
LOW POWER
MODE
PULL
LOW
ALLOW
PCIE
Gen2
PULL
HIGH
LPC_CLK0 LPC_CLK1
FORCE
PCIE
Gen1
DEB UG STRAPS
R 28 0
10 K_ 04
PCI_CLK1
R 60 9
*2. 2 K_ 04
R 27 7
*10 K _0 4
E XT
R 36 0
*10 K _0 4
D E F A U LT
R 27 8
10 K _0 4
I N T
DISABLE ILA
AUTORUN
R 59 3
*1 0K _0 4
R 61 4
* 2. 2 K_ 04
R 3 94
* 10 K_ 04
R 62 1
* 10 K_ 04
USE
DE
BUG
STRAP
REQ UIR ED
STRAPS
R 3 91
* 2. 2K _ 04
R 64 9
1 0K _ 04
E NABLE PCI
ME M BOOT
AZ_SDOUT PCI_CLK2
R 65 1
* 10 K_ 04
PCI_AD26
GPIO199
L,H = LPC ROM ( Default)
R 5 87
10 K _0 4
D EF A U L T
PERFORMANCE
MODE
PCI_AD27
R 3 92
1 0K _ 04
R 3 90
* 10 K_ 04
PCI_AD23
H,H = Reserved
H,L = SPI ROM
L,L = F WH ROM
D EF A U L T
Use 2.2K PD.
Watchdo g
T im er
Dis abled
non_F u sion
CLOCK
MODE
BYPASS
PCI PLL
R 60 7
*10 K _0 4
R 65 3
*10 K _0 4
R 61 3
*2. 2 K _0 4
R 59 2
2. 2 K _0 4
R 65 7
*10 K _0 4
R 62 6
* 2. 2 K_ 04
R 38 7
*10 K _0 4
R 65 2
10 K_ 04 R 6 02
*1 0 K_ 04
R 62 7
* 10 K_ 0 4
R 28 1
*10 K _0 4
R 36 2
10 K_ 04
R 61 1
*10 K _0 4
R 6 03
1 0K _ 04 R 5 86
*2 . 2K _0 4
VD D I O _A Z 3 . 3V D U A L 3 . 3V D U A L
3 . 3V S 3 . 3V S 3 . 3V S 3. 3 VS 3. 3V S
3. 3V S
3 .3 V D U A L
3 . 3V S 3 . 3V S 3. 3V S
3 . 3V D U A L
D D R 1 . 5V _ PW R GD 3 8
P C I _ C LK 2 22
P C I _ C LK 4 22
L P C _C L K 0 22
P C I _ C LK 3 22
L P C _C L K 1 20 , 22
P C L K_ K B C 22 , 33
P C I _A D 2 6 22
P C I _A D 2 4 22
P C I _A D 2 5 22
P C I _A D 2 3 22
P C I _A D 2 7 22
GP I O 19 9 23
GP I O 20 0 23
3. 3 VS 3. 3 VS
P C I E _ WA K E _U P # 23
K B C _ LOW _ BA T # 23
R TC _ C LK 22
SW I # 23 , 33
OD D _ P LU GI N # 2 3, 2 7
IR _R X 1 23
G BE _ P H Y _S T AT 0
23
P C I E _ EX P C A R D _P W R E N # 23
LD R Q# 0 22
E C _A 2 0M# 23 , 33
C PU _T H ER MTR I P # 4 , 23
U SB 3 0_ P WR _ E N 23 , 32
I MC _L C D _ B KL _P W M 2 1, 2 3
C PU _ ME MH OT # 4 , 11 , 23
E C _S C I # 23 , 33
SB _ BL I N K 23
EC _ S MI # 23 , 33
L A D 3 20 , 22 , 33
L A D 2 20 , 22 , 33
L A D 1 20 , 22 , 33
L A D 0 20 , 22 , 33
1 .2 V _P W R GD 4 0
S E R I R Q 2 0, 2 2, 3 3
D 3 7 *R B 7 51 V
A C