Clevo PB70DDS, Service Manual

Page: 96 / 132

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DESIGN NOTE:PEQ
Programmalbe input equalization levels;
internal pull down at~150k, 3.3V I/O
L: default, LEQ, compensate channel loss up to 12dB at HBR2
H: HEQ, compensate channel loss up to 15dB at HBR2
M:LLEQ, compensate channel loss up to 5dB at HBR2
DESIGN NOTE:CFG0
Configuration pin for automatic EQ and Aux interception;
Internal pull down at ~150Kohm,3.3V I/O
L: default, automatic EQ enable and Aux interception enable
H: automatic EQ disable and AUX interception enable
M: automatic EQ disable and AUX interception disable,no pre-emphasis, 600mVpp swing
DESIGN NOTE:CFG1
Configuration pin for auto test and input offset cancellation;
internal pull up at~150K,3.3V IO
H: default, auto test disable and input offset cancellation enable
L: auto test enable and input offset cancellation enable
M: auto test disable and input offset cancellation disable
From NV Port_A
From NV Port_A
From TBT
To TBT
PDB PIN:
L:Chip power down
H:Normal operation(default)
close PS8330B
To TBT
mDP REDRIVER
To NV Port_A
DIFF=90ohm, Total L<6"
DIFF=100ohm, L<2"
DIFF=100ohm, L<2" DIFF=90ohm, Total L<6"
use non-dongle Cable, TBT no display
PS8330B_AUXn
PS8330B_AUXp
PS8330B_CFG0
PS8330B_CFG1
CEXT
PS8330B_PEQ
PS8330_REXT
IN0P_R
IN0N_R
IN1N_R
IN1P_R
IN2N_R
IN2P_R
IN3N_R
IN3P_R
3.3VS
3.3VS
3.3VS
3.3VS
3.3VS
3.3VS
3.3VS
3.3VS [8,9,10,11,12,28,32,33,35,36,37,38,41,42,43,44,45,47,54,56,57,58,59,63,64,70]
PS8330B_AUXn_SDA [46]
PS8330B_AUXp_SCL [46]
MDP_A0 [26]
MDP_A2 [26]
MDP_A#1 [26]
MDP_A1 [26]
MDP_A#0 [26]
MDP_A#3 [26]
MDP_A3 [26]
MDP_A#2 [26]
MDP_A_AUX#_SDA [26]
MDP_A_AUX_SCL [26]
MDP_A_TBT_HPD [32]
DGPU_PW R_EN [32,37,42]
PS8330B_HPD [37,46]
PS8330B_D3N [46]
PS8330B_D3P [46]
PS8330B_D2N [46]
PS8330B_D2P [46]
PS8330B_D1N [46]
PS8330B_D1P [46]
PS8330B_D0N [46]
PS8330B_D0P [46]
Title
Size Document Number R e v
Date: Sheet o f
6-71-PB5D0-D02
D02
[49] TBT DP REPEATER PS8330B
A3
49 84 Tuesday, December 17, 2019
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
PB50DF2
Title
Size Document Number R e v
Date: Sheet o f
6-71-PB5D0-D02
D02
[49] TBT DP REPEATER PS8330B
A3
49 84 Tuesday, December 17, 2019
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
PB50DF2
Title
Size Document Number R e v
Date: Sheet o f
6-71-PB5D0-D02
D02
[49] TBT DP REPEATER PS8330B
A3
49 84 Tuesday, December 17, 2019
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
PB50DF2
R224 *4.7K_04 W / TBT PS8330
C967 0.1u_10V_X7R_04 W / TBT PS8330
C882 0.1u_10V_X7R_04 W / TBT PS8330
R223 *4.7K_04 W / TBT PS8330
R192
100K_04
W / TBT PS8330
C927
0.1u_6.3V_X5R_02
W / TBT PS8330
R225 *4.7K_04 W / TBT PS8330
C988
0.01u_16V_X7R_04
W / TBT PS8330
C956 0.1u_10V_X7R_04 W / TBT PS8330
R196 0_04 W / TBT PS8330
C934 0.1u_10V_X7R_04 W / TBT PS8330
R760 *4.7K_04 W / TBT PS8330
R194 0_04
W / TBT PS8330
C947 0.1u_10V_X7R_04 W / TBT PS8330
R756 *4.7K_04 W / TBT PS8330
R189 0_04 W / TBT PS8330
R227 4.99K_1%_04 W / TBT PS8330
R238
1M_04
W / TBT PS8330
C1378
2.2u_6.3V_X5R_04
W / TBT PS8330
C898 0.1u_10V_X7R_04 W / TBT PS8330
C980 0.1u_10V_X7R_04 W / TBT PS8330
R226 *4.7K_04 W / TBT PS8330
C942 0.1u_10V_X7R_04 W / TBT PS8330
C971 0.1u_10V_X7R_04 W / TBT PS8330
R659 10K_04 W / TBT PS8330
C996 2.2u_6.3V_X5R_04
W / TBT PS8330
C960 0.1u_10V_X7R_04 W / TBT PS8330
R193
100K_04
W / TBT PS8330
PS8330B
U16
PS8330B
W / TBT PS8330
VDD3
3
1
CEXT
2
I2
C_
ADD
R
3
S
C
L_
C
T
LP
E
Q
4
SDA
_
CL
T
C
F
G
0
5
VDD3
3
6
REXT
7
CAD_
SRC
8
HPD_
SRC
9
CAD_
SNK
10
HPD_
SNK
11
VDD3
3
12
OUT3n
13
OUT3p
14
NC
15
OUT2n
16
OOUT2p
17
GND
18
OUT1n
19
OUT1p
20
NC
21
OUT0n
22
OUT0p
23
GND
24
VDD3
3
36
RST
#
35
SD
A_
DDC
34
SC
L
_
DDC
33
VDD3
3
32
GN
D
31
A
U
X_
SR
Cp
30
A
U
X_
SR
Cn
29
AU
X_
SN
Kp
28
AU
X_
SN
Kn
27
PD
#
26
VDD3
3
25
IN3n
48
IN3p
47
NC
46
IN2n
45
IN2p
44
NC
43
IN1n
42
IN1p
41
CFG1
40
IN0n
39
IN0p
38
NC
37
EPAD
49
Sheet 49 of 85
PS8330B
Schematic Diagrams
B - 50 PS8330B
B.Schematic Diagrams
PS8330B