DS245F4
9
CS8420
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS
Inputs: Logic 0 = 0 V, Logic 1 = VD+; C
L
= 20 pF.
7.
The active edges of ISCLK and OSCLK are programmable.
8.
When OSCLK, OLRCK, ISCLK, and ILRCK are derived from OMCK they are clocked from its rising edge.
When these signals are derived from RMCK, they are clocked from its falling edge.
9.
The polarity of ILRCK and OLRCK is programmable.
10. No more than 128 SCLK per frame.
11. This delay is to prevent the previous I/OSCLK edge from being interpreted as the first one after I/OLRCK
has changed.
12. This setup time ensures that this I/OSCLK edge is interpreted as the first one after I/OLRCK has changed.
Parameter
Symbol Min Typ
Max
Units
OSCLK Active Edge to SDOUT Output Valid
t
dpd
-
-
25
ns
SDIN Setup Time Before ISCLK Active Edge
t
ds
20
-
-
ns
SDIN Hold Time After ISCLK Active Edge
t
dh
20
-
-
ns
Master Mode
O/RMCK to I/OSCLK active edge delay
t
smd
0
-
16
ns
O/RMCK to I/OLRCK delay
t
lmd
0
-
17
ns
I/OSCLK and I/OLRCK Duty Cycle
-
50
-
%
Slave Mode
I/OSCLK Period
t
sckw
36
-
-
ns
I/OSCLK Input Low Width
t
sckl
14
-
-
ns
I/OSCLK Input High Width
t
sckh
14
-
-
ns
I/OSCLK Active Edge to I/OLRCK Edge
t
lrckd
20
-
-
ns
I/OLRCK Edge Setup Before I/OSCLK Active Edge
t
lrcks
20
-
-
ns
t
ILRCK
OLRCK
(input)
ISCLK
OSCLK
(input)
SDIN
SDOUT
t
lrckd
lrcks
t
sckh
t
sckw
t
sckl
tdpd
dh
t
ds
t
t
sm d
t
lm d
H ardware M ode
Softw are M ode
ISC LK
O SC LK
(output)
ILR C K
O LR C K
(output)
R M C K
(output)
R M C K
(output)
O M CK
(input)
Figure 1. Audio Port Master Mode Timing
Figure 2. Audio Port Slave Mode and Data Input Timing
