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DS245F4

39

CS8420

10.7

Serial Audio Output Port Data Format (06h)

SOMS

Master/Slave Mode Selector
0 - Serial audio output port is in Slave mode (default)
1 - Serial audio output port is in Master mode

SOSF

OSCLK frequency (for Master mode)
0 - 64*Fso (default)
1 - 128*Fso

SORES[1:0]

Resolution of the output data on SDOUT and AES3 output when the sample rate converter is
set as the source
00 - 24 bit resolution (default)
01 - 20 bit resolution
10 - 16 bit resolution
11 - Direct copy of the received NRZ data from the AES3 receiver (including C, U, and
V bits, the time slot normally occupied by the P bit is used to indicate the location
of the block start, SDOUT pin only, serial audio output port clock must be derived
from the AES3 receiver recovered clock)

SOJUST

Justification of SDOUT data relative to OLRCK
0 - Left-Justified (default)
1 - Right-Justified (Master mode only)

SODEL

Delay of SDOUT data relative to OLRCK, for left-justified data formats
0 - MSB of SDOUT data occurs in the first OSCLK period after the OLRCK edge
(default)
1 - MSB of SDOUT data occurs in the second OSCLK period after the OLRCK edge

SOSPOL

OSCLK clock polarity
0 - SDOUT transitions occur on falling edges of OSCLK (default)
1 - SDOUT transitions occur on rising edges of OSCLK

SOLRPOL

OLRCK clock polarity
0 - SDOUT data is for the left channel when OLRCK is high (default)
1 - SDOUT data is for the right channel when OLRCK is high

7

6

5

4

3

2

1

0

SOMS

SOSF

SORES1

SORES0

SOJUST

SODEL

SOSPOL

SOLRPOL

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Summary of Contents for CS8420

Page 1: ...ffers making read modify write cycles easy Digital audio inputs and outputs may be 24 20 or 16 bits The input data can be completely asynchronous to the output data with the output data being synchronous to an external system clock The CS8420 is available in a 28 pin SOIC package in both Commercial 10º to 70º C and Automotive grades 40º to 85º C The CDB8420 Customer Dem onstration board is also av...

Page 2: ...respect to 0 V Operation beyond these limits may result in permanent dam age to the device Normal operation is not guaranteed at these extremes Notes 1 Transient currents of up to 100 mA will not cause SCR latch up Parameter Symbol Min Typ Max Units Power Supply Voltage VD VA 4 75 5 0 5 25 V Ambient Operating Temperature Commercial Grade Automotive Grade TA 10 40 70 85 C C Parameter Symbol Min Max...

Page 3: ...i 1 7 1 kHz 1 dBFS 0 33 Fso Fsi 3 10 kHz 1 dBFS 0 33 Fso Fsi 1 7 10 kHz 1 dBFS 0 33 Fso Fsi 3 THD N 117 112 110 107 dB dB dB dB Peak idle channel noise component 140 dBFS Resolution 16 24 bits Gain Error 0 12 0 dB Parameter Symbol Min Typ Max Units Passband Upsampling Downsampling 0 0 0 4535 Fsi 0 4535 Fso Hz Hz Passband Ripple 0 007 dB Stopband Downsampling 0 5465 Fso Fsi 2 Hz Stopband Attenuatio...

Page 4: ...tput Voltage IOH 21 mA TXP TXN VD 0 7 V Low Level Output Voltage IOH 21 mA TXP TXN 0 7 V High Level Input Voltage except RXP RXN VIH 2 0 VD 0 3 V Low Level Input Voltage except RXP RXN VIL 0 3 0 8 V Parameters Symbol Typ Units TXP Output Resistance RTXP 25 Ω TXN Output Resistance RTXN 25 Ω Parameter Symbol Min Typ Max Units RST pin Low Pulse Width 200 μs OMCK Frequency for OMCK 512 Fso 4 096 55 3 ...

Page 5: ...nits OSCLK Active Edge to SDOUT Output Valid Note 7 tdpd 25 ns SDIN Setup Time Before ISCLK Active Edge Note 7 tds 20 ns SDIN Hold Time After ISCLK Active Edge Note 7 tdh 20 ns Master Mode O RMCK to I OSCLK active edge delay Note 7 8 tsmd 0 16 ns O RMCK to I OLRCK delay Note 9 tlmd 0 17 ns I OSCLK and I OLRCK Duty Cycle 50 Slave Mode I OSCLK Period Note 10 tsckw 36 ns I OSCLK Input Low Width tsckl...

Page 6: ...uld be safe for all possible conditions 14 Data must be held for sufficient time to bridge the transition time of CCLK 15 For fsck 1 MHz Parameter Symbol Min Typ Max Units CCLK Clock Frequency Note 13 fsck 0 6 0 MHz CS High Time Between Transmissions tcsh 1 0 μs CS Falling to CCLK Edge tcss 20 ns CCLK Low Time tscl 66 ns CCLK High Time tsch 66 ns CDIN to CCLK Rising Setup Time tdsu 40 ns CCLK Risi...

Page 7: ...dition Hold Time prior to first clock pulse thdst 4 0 μs Clock Low Time tlow 4 7 μs Clock High Time thigh 4 0 μs Setup Time for Repeated Start Condition tsust 4 7 μs SDA Hold Time from SCL Falling Note 16 thdd 0 μs SDA Setup Time to SCL Rising tsud 250 ns Rise Time of Both SDA and SCL Lines tr 25 ns Fall Time of Both SDA and SCL Lines tf 25 ns Setup Time for Stop Condition tsusp 4 7 μs tbuf t hdst...

Page 8: ...e OLRCK OSCLK SDOUT Microcontroller SDA CDOUT AD0 CS SCL CCLK AD1 CDIN U INT VA VD Ferrite Bead 5V Analog Supply 5V Digital Supply 0 1 F μ 0 1 F μ A separate analog supply is only necessary in applications where RMCK is used for a jitter sensitive task For applications where RMCK is not used for a jitter sensitive task connect VA to VD via a ferrite bead Keep the decoupling capacitor between VA an...

Page 9: ...is data sheet In these modes flexibility is limited with pins providing some programmability When used for AES3 input AES3 output applications the CS8420 can automatically transceive user data that con forms to the IEC60958 recommended format The CS8420 also allows access to the relevant bits in the AES3 data stream to comply with the serial copy management system SCMS The diagram on the cover of ...

Page 10: ...e ac tually usable Serial Audio Input AES3 Encoder Serial Audio Output Receiver Sample Rate Converter RXP RXN ILRCK ISCLK SDIN OLRCK OSCLK SDOUT TXP TXN AES3 TXOFF AESBP SPD1 0 TXD1 0 SRCD Figure 6 Software Mode Audio Data Flow Switching Options SIMS PLL TXP TXN SDOUT OSCLK OLRCK OMCK RMCK RXP ILRCK ISCLK SDIN MUX MUX MUX SWCLK UNLOCK 0 1 0 1 0 1 CHANNEL STATUS MEMORY USER BIT MEMORY TRANSMIT AES3...

Page 11: ...mption The AESBP data path from the RXP pin to the AES3 output drivers and the TXOFF control have been omitted for clarity but are present and functional in all modes where the AES3 transmitter is in use Figures 8 and 9 show audio data entering via the serial audio input port then passing through the sample rate con verter and then output both to the serial audio output port and to the AES3 transm...

Page 12: ...RXN Serial Audio Input AES3 Encoder Driver Serial Audio Output Sample Rate Converter ILRCK ISCLK SDIN OLRCK OSCLK SDOUT TXP TXN PLL RMCK OMCK TXD1 0 SPD1 0 SRCD OUTC INC RXD1 0 00 00 0 0 0 01 Clock Source Control Bits Data Flow Control Bits AES3 Rx RXP RXN Figure 10 AES3 Input SRC Enabled Figure 11 Serial Audio Input AES3 Input Clock Source Figure 12 Serial Audio Input SRC Output Clocked by AES3 R...

Page 13: ... Control Bits Data Flow Control Bits AES3 Rx Decode RXP RXN Serial Audio Input ILRCK ISCLK SDIN Serial Audio Output OLRCK OSCLK SDOUT PLL RMCK TXD1 0 SPD1 0 SRCD TXOFF OUTC INC RXD1 0 10 10 0 1 1 0 01 Clock Source Control Bits Data Flow Control Bits AES3 Rx Decode RXP RXN Serial Audio Input AES3 Encoder Driver ILRCK ISCLK SDIN TXP TXN OMCK TXD1 0 SPD1 0 SRCD OUTC INC RXD1 0 01 01 0 0 1 00 Clock So...

Page 14: ...ng is used internally where appropriate inside the SRC block The output side of the SRC can be set to 16 20 or 24 bits Optional dithering can be applied and is auto matically scaled to the selected output word length This dither is not correlated between left and right chan nels It is recommended that the dither control bit be left in its default ON state 5 2 SRC Locking Varispeed and the Sample R...

Page 15: ...e serial audio data stream The P bit is replaced by a bit indicating the location of the start of a block This format is only available when the serial audio output port is being clocked by the AES3 receiver recovered clock Also the received channel status block start signal is only available in Hardware mode 5 as the RCBL pin In Master mode the left right clock and the serial bit clock are output...

Page 16: ...B SDIN MSB LSB LSB Right Justified In X don t care to match format but does need to be set to the desired setting I S can accept an arbitrary number of bits determined by the number of ISCLK cycles not 11 See Serial Input Port Data Format Register Bit Descriptions for an explanation of the meaning of each bit SIMS SISF SIRES1 0 SIJUST SIDEL SISPOL SILRPOL Left Justified X X 00 0 0 0 0 I S X X 00 0...

Page 17: ...ft Justified X X XX 0 0 0 0 I S X X XX 0 1 0 1 Right Justified 1 X XX 1 0 0 0 AES3 Direct X X 11 0 0 0 0 OLRCK OSCLK SDOUT Channel A Channel B Left Justified Out OLRCK OSCLK Channel A SDOUT Channel B I S Out OLRCK OSCLK Channel A Channel B MSB SDOUT MSB LSB LSB MSB Extended MSB Extended Right Justified Out OLRCK OSCLK Channel A Channel B MSB SDOUT LSB LSB Channel A Channel B LSB LSB MSB MSB MSB AE...

Page 18: ...ion when input is removed from the Receiver 7 1 3 Error Reporting and Hold Function While decoding the incoming AES3 data stream the CS8420 can identify several kinds of error indicated in the Receiver Error register The UNLOCK bit indicates whether the PLL is locked to the incoming AES3 data The V bit reflects the current validity bit status The CONF confidence bit indicates the amplitude of the ...

Page 19: ...S and U data 7 1 5 User Data Handling The incoming user data is buffered in a user accessible buffer Various automatic modes of re transmit ting received U data are provided Channel Status and User Data Buffer Management on page 81 de scribes the overall handling of CS and U data Received U data may also be output to the U pin under the control of a control register bit Depending on the data flow ...

Page 20: ...nverter This clock may be derived from the clock input pin OMCK or from the incoming data In data flows with no SRC and where OMCK is asynchronous to the data source an interrupt bit is provided that will go high every time a data sample is dropped or repeated The channel status C and user channel U bits in the transmitted data stream are taken from storage areas within the CS8420 The user can man...

Page 21: ...n In this mono mode 2 AES3 cables are needed for stereo data transfer The CS8420 offers mono mode opera tion both for the AES3 receiver and for the AES3 transmitter Figure 21 shows the operation of mono mode in comparison with normal stereo mode The receiver and transmitter sections may be independently set to mono mode via the MMR and MMT control bits The receiver mono mode effectively doubles Fs...

Page 22: ...frame time Thold 0 Tth Tth 3 OMCK if TCBL is Input Tth 3 OMCK if TCBL is Input Tth U Input TCBL In or Out SDIN Input TXP N Output TXP N Output VLRCK VCU Input SDIN Input TCBL In or Out TXP N VLRCK duty cycle is 50 In stereo mode VLRCK frequency AES3 frame rate In mono mode ALRCK frequency 2xAES3 frame rate If the serial audio input port is in master mode and TCBL is an input the VLRCK ILRCK if SIL...

Page 23: ...12x 96kHz A B sub frames data are time multiplexed into consecutive samples Consecutive samples are alternately routed to A B sub fames RECEIVER MONO MODE RECEIVER STEREO MODE MMTLR TRANSMITTER STEREO MODE TRANSMITTER MONO MODE A1 B1 Outgoing AES3 SRC Aout SRC Bout A1 B1 A2 B2 STEREO MONO Frame A2 B2 Outgoing AES3 A selected Outgoing AES3 B selected A1 A2 B1 B2 Frame TRANSMITTER TIMING Figure 21 M...

Page 24: ... all of the parts TCBL on one of the CS8420 parts should be set as an output while the remaining TCBL pins should be set as inputs This synchronizes the AES transmitter on all of the parts Depending upon software considerations it may be advantageous to configure the registers so that an in terrupt is generated on the INT pin when lock occurs The control logic should either poll the unlock bits un...

Page 25: ...elay of 1 frame The 0 5 frame delay in the second half of the equation is due to the startup uncertainty of the logic within the part 1 All inputs are slaves and all outputs are masters both with respect to the outside world 2 The inputs and outputs are synchronous to one another Path Delay in units of a frame RX to TX 3 1 128 Serial Input to TX 2 1 128 RX to Serial Output 3 1 128 Serial Input to ...

Page 26: ...t be 0010000b The eighth bit is a read write indicator R W which should be low to write The next 8 bits form the Memory Address Pointer MAP which is set to the address of the register that is to be updated The next 8 bits are the data which will be placed into the register designated by the MAP During writes the CDOUT output stays in the Hi Z state It may be externally pulled high or low with a 47...

Page 27: ...acknowledge bit The ACK bit is output from the CS8420 after each input byte is read and is input to the CS8420 from the microcon troller after each transmitted byte 9 3 Interrupts The CS8420 has a comprehensive interrupt capability The INT output pin is intended to drive the interrupt input pin on the host microcontroller The INT pin may be set to be active low active high or active low with no ac...

Page 28: ...r 1 Mask 10 Interrupt Register1 Mode MSB 11 Interrupt Register 1 Mode LSB 12 Interrupt Register 2 Mask 13 Interrupt Register 2 Mode MSB 14 Interrupt Register 2 Mode LSB 15 Receiver Channel Status Bits 16 Receiver Error Status 17 Receiver Error Mask 18 Channel Status Data Buffer Control 19 User Data Buffer Control 20 to 29 Q channel Subcode Bytes 0 to 9 30 Sample Rate Ratio 31 Reserved 32 to 55 C b...

Page 29: ...pt 1 Mode MSB TSLIP1 OSLIP1 SRE1 OVRGL1 OVRGR1 DETC1 EFTC1 RERR1 0B Interrupt 1 Mode LSB TSLIP0 OSLIP0 SRE0 OVRGL0 OVRGR0 DETC0 EFTC0 RERR0 0C Interrupt 2 Mask 0 0 VFIFOM REUNLOCKM DETUM EFTUM QCHM UOVWM 0D Interrupt 2 Mode MSB 0 0 VFIFO1 REUNLOCK1 DETU1 EFTU1 QCH1 UOVW1 0E Interrupt 2 Mode LSB 0 0 VFIFO0 REUNLOCK0 DETU0 EFTU0 QCH0 UOVW0 0F Receiver CS Data AUX3 AUX2 AUX1 AUX0 PRO AUDIO COPY ORIG ...

Page 30: ...tput port MUTEAES Mute control for the AES3 transmitter output 0 Normal output default 1 Mute the AES3 transmitter output DITH Dither Control 0 Triangular PDF dither applied to output data The level of the dither is automatically adjusted to be appropriate for the output word length selected by the SORES bits default 1 No dither applied to output data INT 1 0 Interrupt INT output pin control 00 Ac...

Page 31: ...one channel of data This data is duplicated to both left and right parallel outputs of the AES receiver block The input sample rate Fsi is doubled compared to MMR 0 MMT Select AES3 transmitter mono or stereo operation 0 Outputs left channel input into A subframe and right channel input into B subframe normal stereo operation default 1 Output either left or right channel inputs into consecutive sub...

Page 32: ...rial Audio Output Port 0 Disables Auto Mute on loss of lock default 1 Enables Auto Mute on loss of lock TXOFF AES3 Transmitter Output Driver Control 0 AES3 transmitter output pin drivers normal operation default 1 AES3 transmitter output pin drivers drive to 0 V AESBP AES3 bypass mode selection 0 normal operation 1 Connect the AES3 transmitter driver input directly to the RXP pin which become a no...

Page 33: ...atio selector If these bits are changed during normal operation then always stop the CS8420 first RUN 0 then write the new value then start the CS8420 RUN 1 00 OMCK frequency is 256 Fso default 01 OMCK frequency is 384 Fso 10 OMCK frequency is 512 Fso 11 reserved OUTC Output Time Base 0 OMCK input pin modified by the selected divide ratio bits CLK1 CLK0 default 1 Recovered Input Clock INC Input Ti...

Page 34: ...IN data relative to ILRCK 0 Left Justified default 1 Right Justified SIDEL Delay of SDIN data relative to ILRCK for left justified data formats 0 MSB of SDIN data occurs in the first ISCLK period after the ILRCK edge default 1 MSB of SDIN data occurs in the second ISCLK period after the ILRCK edge SISPOL ISCLK clock polarity 0 SDIN sampled on rising edges of ISCLK default 1 SDIN sampled on falling...

Page 35: ...e block start SDOUT pin only serial audio output port clock must be derived from the AES3 receiver recovered clock SOJUST Justification of SDOUT data relative to OLRCK 0 Left Justified default 1 Right Justified Master mode only SODEL Delay of SDOUT data relative to OLRCK for left justified data formats 0 MSB of SDOUT data occurs in the first OSCLK period after the OLRCK edge default 1 MSB of SDOUT...

Page 36: ...his bit will go high every time a data sam ple is dropped or repeated Also when the SRC is used and the SRC output goes to the output serial port configured in Slave mode this bit will indicate if the ratio of OMCK frequency to OL RCK frequency does not match what is set in the CLK1 and CLK0 bits SRE Sample rate range exceeded indicator Occurs if Fsi Fso or Fso Fsi exceeds 3 OVRGL Over range indic...

Page 37: ... for reading The data must be completely read with in 588 AES3 frames after the interrupt occurs to avoid corruption of the data by the next block UOVW U bit FIFO Overwrite This interrupt occurs on an overwrite in the U bit FIFO 10 10 Interrupt 1 Register Mask 09h The bits of this register serve as a mask for the Interrupt 1 Register If a mask bit is set to 1 the error is considered unmasked meani...

Page 38: ...upt Register 2 This register de faults to 00 10 13 Interrupt Register 2 Mode Registers MSB LSB 0Dh 0Eh The two Interrupt mode registers form a 2 bit code for each Interrupt 2 register function This code deter mines whether the INT pin is set active on the arrival of the interrupt condition on the removal of the interrupt condition or on the continuing occurrence of the interrupt condition These re...

Page 39: ...a is 5 bits long 0110 Auxiliary data is 6 bits long 0111 Auxiliary data is 7 bits long 1000 Auxiliary data is 8 bits long 1001 1111 Reserved PRO Channel status block format indicator 0 Received channel status block is in consumer format 1 Received channel status block is in professional format AUDIO Audio indicator 0 Received data is linearly coded PCM audio 1 Received data is not linearly coded P...

Page 40: ...is bit is valid in Professional mode only 0 No error 1 Error UNLOCK PLL lock status bit Updated on CS block boundaries 0 PLL locked 1 PLL out of lock V Received AES3 Validity bit status Updated on sub frame boundaries 0 Data is valid and is normally linear coded PCM audio 1 Data is invalid or may be valid compressed audio CONF Confidence bit Updated on sub frame boundaries 0 No error 1 Confidence ...

Page 41: ...ns Channel Status data default 1 Data buffer address space contains User data CBMR Control for the first 5 bytes of channel status E buffer 0 Allow D to E buffer transfers to overwrite the first 5 bytes of channel status data default 1 Prevent D to E buffer transfers from overwriting first 5 bytes of channel status data DETCI D to E C data buffer transfer inhibit bit 0 Allow C data D to E buffer t...

Page 42: ...uffer transfers default 1 Inhibit U data E to F buffer transfer Q Channel Subcode Bytes 0 to 9 14h 1Dh Read Only The following 10 registers contain the decoded Q channel subcode data Each byte is LSB first with respect to the 80 Q subcode bits Q 79 0 Thus bit 7 of address 14h is Q 0 while bit 0 of address 14h is Q 7 Similarly bit 0 of address 1Dh corresponds to Q 79 7 6 5 4 3 2 1 0 0 0 0 UD UBM1 U...

Page 43: ...al part of the sample rate ratio 10 20 C Bit or U Bit Data Buffer 20h 37h Either channel status data buffer E or user data buffer E provided UBM bits are set to block mode is ac cessible via these register addresses 10 21 CS8420 I D and Version Register 7Fh Read Only ID 3 0 ID code for the CS8420 Permanently set to 0001 VER 3 0 CS8420 Revision Level Revision B is coded as 0001 Revision C is coded ...

Page 44: ...it for the control port in I C mode Hardware modes use many start up options which are detailed in the hardware definition section at the end of this data sheet 11 2 Transmitter Startup When the CS8420 is taken out of power down and the AES3 receiver is configured to be in circuit the part uses the clock recovered from the AES3 input stream to advance its internal state machine to run This can be ...

Page 45: ...0 μs and then set it high again This action clears the invalid state if it has occurred When polling the RERR pin again the user must account for the fact that the RERR pin will be high during reset and remain high until the PLL has reachieved lock In either Software or Hardware mode when clearing the invalid state it is advisable to mute any devices connected to the output of the CS8420 11 4 C U ...

Page 46: ... 5V supply for VA decoupled to AGND In addition a separate region of analog ground plane around the FILT AGND VA RXP and RXN pins is recommended The VD supply should be well decoupled with a 0 1 μF capacitor to DGND to minimize AES3 transmitter induced transients Extensive use of power and ground planes ground plane fill in unused areas and surface mount decoupling capacitors are recommended Make ...

Page 47: ...V VA Positive Analog Power Positive supply for the analog section Nominally 5 0 V This supply should be as quiet as possible since noise on this pin will directly affect the jitter performance of the recovered clock DGND Digital Ground Ground for the digital section DGND should be connected to the same ground as AGND AGND Analog Ground Ground for the analog section AGND should be connected to the ...

Page 48: ...ble via a control register The polarity of the INT output as well as selection of a standard or open drain output is set via a control register Once set true the INT pin goes false only after the interrupt status registers have been read and the interrupt status bits have re turned to zero Audio Input Interface SDIN Serial Audio Input Port Data Input Audio data serial input pin ISCLK Serial Audio ...

Page 49: ... operated as input driving TCBL high for at least three OMCK or RMCK depending on which clock is operating the AES3 encoder block clocks will cause the next transmitted sub frame to be the start of a channel status block TXN TXP Differential Line Driver Outputs Differential line driver outputs transmitting AES3 type data Drivers are pulled to low while the CS8420 is in the reset state Control Port...

Page 50: ...e the default state of the UD direction bit sets the U pin as an input The pull down resistor ensures that the transmitted user data will be zero If the U pin is always set to be an output thereby causing the U bit manager to be the source of the U data the resistor is not necessary The U pin should not be tied directly to ground in case it is programmed to be an output and subsequently tries to o...

Page 51: ...ormats In Hardware mode only a limited number of alternative serial audio port formats are available These for mats are described by Tables 6 and 7 which define the equivalent Software mode bit settings for each format Timing diagrams are shown in Figures 17 and 18 For each Hardware mode the following pages contain a data flow diagram a pin out drawing a pin de scriptions list and a definition of ...

Page 52: ... choice of four serial audio output port formats and the source for transmitted C U and V data The following pages contain the detailed pin descriptions for Hardware mode 1 If a validity parity bi phase or lock receiver error occurs the current audio sample will be held SDOUT RMCK RERR COPY Function LO Serial Output Port is Slave HI Serial Output Port is Master LO Mode1A C transmitted data is copi...

Page 53: ...normally If MUTE is high both the AES3 transmitted audio data and the serial audio output port data is set to digital zero OMCK Output Section Master Clock Input Output section master clock input The frequency must be 256x the output sample rate Fso AES3 SPDIF Receiver Interface RXP RXN Differential Line Receiver Inputs Differential line receiver inputs carrying AES3 type data RMCK Input Section R...

Page 54: ...ssional Consumer Channel Status bit in the incoming AES3 type data stream or is the serial C bit input for the AES3 type transmitted data clocked by OLRCK AUDIO V Audio Channel Status Bit Output or V Bit Data Input The AUDIO V pin either reflects the state of the audio non audio Channel Status bit in the incoming AES3 type data stream or is the V bit data input for the AES3 type transmitted data s...

Page 55: ...PY C ORIG U and EMPH V become serial bit inputs for C U and V data This data is clocked by both edges of OLRCK and the channel status block start is indicated or determined by TCBL Figure 20 shows the timing requirements Audio serial port data formats are selected as shown in Tables 6 7 and 10 Start up options are shown in Table 11 and allow choice of the serial audio output port as a master or sl...

Page 56: ...ction 0 0 Serial Input Output Format IF1 OF1 0 1 Serial Input Output Format IF2 OF2 1 0 Serial Input Output Format IF3 OF3 1 1 Serial Input Output Format IF4 OF3 Table 10 HW Mode 2 Serial Audio Port Format Selection SDOUT LOCK Function LO Serial Output Port is Slave HI Serial Output Port is Master LO TCBL is an input HI TCBL is an output Table 11 Hardware Mode 2 Start Up Options ...

Page 57: ...rmat Select Inputs SFMT0 and SFMT1 select the serial audio input and output ports format See Table 10 OMCK Output Section Master Clock Input Output section master clock input The frequency must be 256x the output sample rate Fso Audio Input Interface SDIN Serial Audio Input Port Data Input Audio data serial input pin ISCLK Serial Audio Input Port Bit Clock Input or Output Serial bit clock for audi...

Page 58: ...s input driving TCBL high for at least three OMCK clocks will cause the current transmitted sub frame to be the start of a channel status block CUVEN C U and V bit Input Enable Mode Input The CUVEN pin determines how the channel status data user data and validity bit is input When CUVEN is low Hardware mode 2A is selected where the EMPH V COPY C and ORIG U pins are used to enter selected channel s...

Page 59: ...a and validity bits are input serially via the PRO C EMPH U and AUDIO V pins Figure 20 shows the timing requirements The serial audio input port is always a slave If a validity parity bi phase or lock receiver error occurs the current audio sample will be held Start up options are shown in Table 12 and allow choice of the serial audio output port as a master or slave whether TCBL is an input or an...

Page 60: ...received PRO EMPH AUDIO is visible HI Mode 3B CUV transmitted data is input serially on pins received PRO EMPH and AUDIO is not visible LO LO Serial Input Output Format IF1 OF1 LO HI Serial Input Output Format IF2 OF2 HI LO Serial Input Output Format IF3 OF3 HI HI Serial Input Output Format IF2 OF4 LO TCBL is an input HI TCBL is an output Table 12 Hardware Mode 3 Start Up Options ...

Page 61: ...ut Audio data serial input pin This data will be transmitted out the AES3 port ISCLK Serial Audio Input Port Bit Clock Input Serial bit clock for audio data on the SDIN pin ILRCK Serial Audio Input Port Left Right Clock Input Word rate clock for the audio data on the SDIN pin The frequency will be at the output sample rate Fso Audio Output Interface SDOUT Serial Audio Output Port Data Output Audio...

Page 62: ... of lock in the PLL This is also a start up option pin and requires a pull up or pull down resistor EMPH U Pre emphasis Indicator Output or U Bit Data Input The EMPH U pin either reflects the state of the EMPH channel status bits in the incoming AES3 type data stream or is the serial U bit input for the AES3 type transmitted data clocked by OLRCK If indicating emphasis EMPH U is low when the incom...

Page 63: ...ts are input serially via the PRO C EMPH U and AUDIO V pins Figure 20 shows the timing requirements The APMS pin allows the serial audio input port to be set to master or slave If a validity parity bi phase or lock receiver error occurs the current audio sample is passed unmodified to the serial audio output port Start up options are shown in Table 13 and allow choice of the serial audio output po...

Page 64: ...received PRO EMPH AUDIO is visible HI Mode 4B CUV transmitted data is input serially on pins received PRO EMPH and AUDIO is not visible LO LO Serial Input Output Format IF1 OF1 LO HI Serial Input Output Format IF2 OF2 HI LO Serial Input Output Format IF3 OF3 HI HI Serial Input Output Format IF1 OF5 LO TCBL is an input HI TCBL is an output Table 13 Hardware Mode 4 Start Up Options ...

Page 65: ... Port Bit Clock Input or Output Serial bit clock for audio data on the SDIN pin ILRCK Serial Audio Input Port Left Right Clock Input or Output Word rate clock for the audio data on the SDIN pin The frequency will be at the input sample rate Fsi APMS Serial Audio Input Port Master or Slave APMS should be connected to VD to set serial audio input port as a master or connected to DGND to set the port...

Page 66: ...arity error and bi phase coding error as well as loss of lock in the PLL This is also a start up option pin and requires a pull up or pull down resistor EMPH U Pre emphasis Indicator Output or U Bit Data Input The EMPH U pin either reflects the state of the EMPH channel status bit in the incoming AES3 type data stream or is the serial U bit input for the AES3 type transmitted data clocked by OLRCK...

Page 67: ...o output port as a master or slave and the serial audio port format The following pages contain the detailed pin descriptions for Hardware mode 5 SDOUT ORIG EMPH Function LO Serial Output Port is Slave HI Serial Output Port is Master LO LO Serial Output Format OF1 LO HI Serial Output Format OF2 HI LO Serial Output Format OF3 HI HI Serial Output Format OF5 Table 14 Hardware Mode 5 Start Up Options ...

Page 68: ...aster Clock Input Output section master clock input This pin is not used in this mode and should be connected to DGND Audio Output Interface SDOUT Serial Audio Output Port Data Output Audio data serial output pin This is also a start up option pin and requires a pull up or pull down resistor OSCLK Serial Audio Output Port Bit Clock Input or Output Serial bit clock for audio data on the SDOUT pin O...

Page 69: ... the COPY Channel Status bit in the incoming AES3 type data stream ORIG Original Channel Status Output SCMS generation indicator This is decoded from the incoming category code and the L bit A low output indicates that the audio data stream is 1st generation or higher A high indicates that the audio data stream is original This is also a start up option pin and requires a pull up or pull down resi...

Page 70: ...ed when the CEN pin is high In mode 6B the channel status user data and validity bit are input serially via the COPY C U and V pins These pins are clocked by both edges of ILRCK if the port is in Master mode Figure 20 shows the timing requirements The channel status block pin TCBL may be an input or an output determined by the state of the TCBLD pin The serial audio input port data format is selec...

Page 71: ...Y C ORIG Function 0 0 PRO 0 COPY 0 L 0 0 1 PRO 0 COPY 0 L 1 1 0 PRO 0 COPY 1 L 0 1 1 PRO 1 Table 15 HW 6 COPY C and ORIG Pin Function SFMT1 SFMT0 Function 0 0 Serial Input Format IF1 0 1 Serial Input Format IF2 1 0 Serial Input Format IF3 1 1 Serial Input Format IF4 ...

Page 72: ...ect the serial audio input port format See Table 15 OMCK Output Section Master Clock Input Output section master clock input The frequency must be 256x the output sample rate Fso Audio Input Interface SDIN Serial Audio Input Port Data Input Audio data serial input pin ISCLK Serial Audio Input Port Bit Clock Input or Output Serial bit clock for audio data on the SDIN pin Pins which remain the same ...

Page 73: ...are set to 000 indicating no pre emphasis COPY C COPY Channel Status Bit Input or C Bit Input In mode 6B the COPY C pin determines the state of the COPY PRO and L Channel Status bits in the outgoing AES3 type data stream See Table 15 In mode 6A the COPY C pin becomes the direct C bit input data pin ORIG ORIG Channel Status Bit Input In mode 6B the ORIG pin determines the state of the COPY PRO and ...

Page 74: ...the circuit in Figure 30 the output of the transformer is short circuit protected has the proper source impedance and provides a 5 volts peak to peak signal into a 110 Ω load Lastly the two output pins should be attached to an XLR connector with male pins and a female shell and with pin 1 of the connector grounded In the case of consumer use the IEC60958 specifications call for an unbalanced drive...

Page 75: ...pin RXP and RXN as shown in Figure 34 However if a transformer is not used high frequency energy could be coupled into the receiver causing degradation in analog performance Figures 33 and 34 show an optional DC blocking capacitor 0 1 μF to 0 47 μF in series with the cable input This improves the robustness of the receiver preventing the saturation of the transformer or any DC current flow if a DC...

Page 76: ...f 25 kHz to 108 kHz after bi phase mark encoding Transformers provide isolation from ground loops 60 Hz noise and common mode noise and interference One of the important considerations when choos ing transformers is minimizing shunt capacitance between primary and secondary windings The higher the shunt capacitance the lower the isolation between primary and secondary and the more coupling of high...

Page 77: ...The buffering scheme involves a cascade of three block sized buffers named D E and F as shown in Figure 37 The MSB of each byte represents the first bit in the serial C data stream For example the MSB of byte 0 which is at control port address 20h is the consumer professional bit for channel status block A The first buffer D accepts incoming C data from the AES receiver The 2nd buffer E accepts en...

Page 78: ...E data without having to inhibit the next transfer For writing the sequence starts after a E to F transfer which is based on the out put timebase Since a D to E transfer could occur at any time this is based on the input timebase then it is important to inhibit D to E transfers while writing to the E buffer until all writes are complete Then wait until the next E to F transfer occurs before enabli...

Page 79: ...gement System SCMS In Software mode the CS8420 allows read modify write access to all the channel status bits For Con sumer mode SCMS compliance the host microcontroller needs to read and manipulate the Category Code Copy bit and L bit appropriately In Hardware mode the SCMS protocol can be followed by either using the COPY and ORIG input pins or by using the C bit serial input pin These options a...

Page 80: ...ll cause the CS8420 to output two bytes from its control port The first byte out will represent the A channel status data and the 2nd byte will represent the B channel status data Writing is similar in that two bytes must now be input to the CS8420 s control port The A channel status data is first B channel status data second 15 2 AES3 User U Bit Management The CS8420 U bit manager has four operat...

Page 81: ...f each IU must be transceived unlike the audio samples there can be no sample rate conver sion of the U data Therefore there are two potential problems 1 Message Partitioning When Fso Fsi more data is transmitted than received per unit time The FIFO will frequently be com pletely emptied Sensible behavior must occur when the FIFO is empty otherwise a single incoming mes sage may be erroneously par...

Page 82: ...mple 1 Fsi Fso 2 N 4 IF 1 minimum proper padding is 53 bits Example 2 Fsi Fso 1 N 4 IF 7 min proper padding is 9 bits The CS8420 detects when an overwrite has occurred in the FIFO and synchronously resets the entire FIFO structure to prevent corrupted U data from being merged into the transmitted AES3 data stream The CS8420 can be configured to generate an interrupt when this occurs Mode 4 is reco...

Page 83: ...sample rate of the input subsequently changes for example in a varispeed application the PLL will only track up to 12 5 from the nominal center sample rate The nominal center sample rate is the sample rate that the PLL first locks onto upon application of an AES3 data stream or after enabling the CS8420 clocks by setting the RUN control bit If the 12 5 sample rate limit is exceeded the PLL will re...

Page 84: ... analog supply voltage The 0 1 µF bypass capacitor is in a 1206 form factor RFILT and the other three capacitors are in an 0805 form factor The traces are on the top surface of the board with the IC so that there is no via inductance The traces themselves are short to minimize the inductance in the filter path The VA and AGND traces extend back to their origin and are shown only in truncated form ...

Page 85: ...ocking to the ILRCK input Also note that many factors can affect jitter performance in a system Please follow the circuit and layout recommendations outlined previously 16 3 3 Locking to the ILRCK Input CS8420 parts that are configured to lock to the ILRCK input should use the external PLL component val ues listed in Table 20 Note that parts that need to lock to both ILRCK and RXP RXN should use t...

Page 86: ...the CS8420 when used with the appropriate external PLL component values as noted in Table 19 The AES3 and IEC60958 4 specifications do not have allowances for locking to sample rates less than 32 kHz or for lock ing to the ILRCK input These specifications state a maximum of 2 dB jitter gain or peaking Figure 43 Jitter Tolerance Template 10 1 10 0 10 1 10 2 10 3 10 4 10 5 20 15 10 5 0 5 Jitter Freq...

Page 87: ...to 0 dBFS Peak Idle Channel Noise Component With an all zero input what is the amplitude of the largest frequency component visible with a 16K point FFT The value is in dB ratio to full scale Input Jitter Tolerance The amplitude of jitter on the AES3 stream or in the ILRCK clock that will cause measurable artifacts in the SRC output Test signal is full scale 9 kHz Fsi is 48 kHz Fso is different 48...

Page 88: ...0 020 0 33 0 51 C 0 009 0 013 0 23 0 32 D 0 697 0 713 17 70 18 10 E 0 291 0 299 7 40 7 60 e 0 040 0 060 1 02 1 52 H 0 394 0 419 10 00 10 65 L 0 016 0 050 0 40 1 27 0 8 0 8 Parameter Symbol Min Typ Max Units Junction to Ambient thermal impedance 28 pin SOIC θJA 65 C W Allowable Junction Temperature TJ 135 C 28L SOIC 300 MIL BODY PACKAGE DRAWING D H E b A1 A c L SEATING PLANE 1 e ...

Page 89: ...ocking to ILRCK on page 28 Revised SRC Invalid State on page 49 PP5 Added DS package to front page Added DS package to Ambient Operating Temperature on page 6 Corrected tdpd on page 9 Corrected tlmd on page 9 Corrected tsmd on page 9 Corrected tdh on page 10 Added C U Buffer Data Corruption on page 49 PP6 Added lead free ordering information F1 Final Release 1 Changed format of Figure 17 on page 2...

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