Cirrus Logic CS4953xx, Hardware User Manual

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3-1 Copyright 2008 Cirrus Logic, Inc. DS732UM7
Serial Control Port Configuration
CS4953xx Hardware Users Manual
Chapter 3
Serial Control Port
The CS4953xx uses the Serial Control Port (SCP) to communicate with external devices such as host
microprocessors using either I
2
C or SPI serial communication formats. Each port can be configured as either a
master or slave. The CS4953xx DSP serial port communicates using the SCP_CLK, SCP_MOSI, and SCP_MISO
(SPI serial master and slave modes), and SCP_SDA (for I
2
C serial master and slave modes) pins.
In both SPI and I
2
C modes, the serial control port performs 8-bit transfers and is always configured as a slave for
external device-controlled data transfers. As a slave, it cannot drive the clock signal nor initiate data transfers. The
port can request a read from the host by activating the SCP1_IRQ pin. The port can also indicate that the host should
stop sending data by activating the SCP1_BSY pin.
It is very important for the host to obey the SCP1_BSY pin status. Messages sent to the DSP’s host control port
(SCP1) when SCP1_BSY pin is low will be lost.
The serial control port can be operated simultaneously with the CS4953xx parallel control port.
The CS4953xx SPI and I
2
C serial communication modes are identical from a functional standpoint. The main
difference between the two is the actual protocol being implemented between the CS4953xx and the host. In
addition, the I
2
C slave has a true I
2
C mode that utilizes data flow mechanisms inherent to the I
2
C protocol. If this
mode is enabled, the I
2
C slave will hold SCP1_CLK low to delay a transfer as needed -- this is in addition to
activating SCP1_BSY.
The CS4953xx has two serial ports. However, the O/S currently supports only slave mode host communication on
SCP1, and master mode communication on SCP2 for booting from a serial EEPROM/FLASH.
3.1 Serial Control Port Configuration
The serial control port configuration for an operating mode is determined by the state of special boot mode pins as
the CS4953xx exits reset. The rising edge of the RESET pin samples the HS[4:0] pins to determine the
communication mode and boot style. The CS4953xx O/S currently supports two serial control port configurations
for host control:
• I
2
C Slave (Write Address = 0x80, Read Address = 0x81)
• SPI Slave (Write Address = 0x80, Read Address = 0x81)
The HS[4:0] signals latched by RESET are read by the boot ROM code to determine the format (SPI slave or I
2
C
slave). The ROM code then configures the serial control port into slave mode and looks for the BOOT_START
message. Please see
Chapter 2, "Operational Modes" for additional details on configuring CS4953xx ports and
communication modes.
Procedures for configuring the serial control port for SPI and I
2
C communication modes are provided in this chapter.