Audio Clocking
CDB47xxx User’s Manual
DS886DB9
Copyright 2012 Cirrus Logic, Inc
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1.5 Audio Clocking
Clocking architecture is one of the most important aspects of an audio system. This can also be one of the
most complicated parts of a system design to insure that clocking is valid and stable for all scenarios. This
is one of the major advantages of the CS470xx Audio System On-a-Chip (ASOC). Because of the
integrated ADC and DAC along with the integrated SRCs, the CS470xx makes audio clocking very
simple. For analog-only systems, the clocking architecture is as simple as a crystal feeding the CS470xx.
Traditionally the input and output clock domains of the DSP needed to be synchronous when delivering
audio data in an isochronous fashion (constant bitrate delivery), even if the input/output domains operate
at different frequencies (e.g. 48 kHz input/96 kHz output). Systems utilizing serial audio data (I
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S) delivery
would thus use isochronous delivery.
The CS470xx’s integrated SRCs remove this requirement because the CS470xx can rate match the input
(DAI) Fs to any Fs on the output side (DAO). The examples below show configurations that support an Fs
that is synchronized between DAI and DAO, as well as an output Fs that is independent of the input Fs.
1.5.1 Clock and Data Flow for ADC Input
Figure 1-8. ADC Clocking
The ADC clocking architecture is used when the internal ADCs are used as the only audio input (that is,
SPDIF is disabled and there are no serial audio signals connected to DAI or DAO). In this scenario, the
CS470xx has all audio clocking self contained.
illustrates this clocking configuration.
The clock fed to XTI of the CS470xx is MCLK for the system, and the ASOC masters clocks to DAC and
ADC. The user need only route in analog signals and route out the processed analog signals.
