Cirrus Logic CDB43L22 Manual Download Page 25 | Manualshive

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DS79

2DB1

25

CDB43L22

Figure 15. Top-Side Layer

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Summary of Contents for CDB43L22

Page 1: ...ing can be provided by the CS8416 by the CS43L22 with supplied master clock or via an I O stake header with a DSP connected 1 8th inch audio jacks are provided for the analog passthrough inputs and HP Line outputs Two pairs of banana jacks and an ad ditional pair of 1 8th inch audio jacks are provided to monitor the stereo differential speaker PWM output from the CS43L22 Digital input connections ...

Page 2: ... 7 CDB43L22 BLOCK DIAGRAM 19 8 CDB43L22 SCHEMATICS 20 9 CDB43L22 LAYOUT 24 10 PERFORMANCE PLOTS 29 11 REVISION HISTORY 31 LIST OF FIGURES Figure 1 SPDIF In to Headphone or Line Out 8 Figure 2 SPDIF In to Stereo Speaker Out 9 Figure 3 SPDIF In to Mono Speaker Out 10 Figure 4 Board Configuration Tab 12 Figure 5 Passthrough Power and Serial Audio Interface Configuration Tab 13 Figure 6 DSP Engine Tab...

Page 3: ...S PDIF In to Speaker Out 60 dBFS 30 Figure 27 Frequency Response S PDIF In to Speaker Out 30 Figure 28 THD N S PDIF In to Speaker Out 30 Figure 29 THD N vs Output Power Stereo 30 Figure 30 THD N vs Output Power Mono 30 LIST OF TABLES Table 1 SPDIF In to Headphone or Line Out Performance Plots 8 Table 2 SPDIF In to Stereo Speaker Out Performance Plots 9 Table 3 SPDIF In to Mono Speaker Out Performa...

Page 4: ...be in the range of 2 7 V to 5 25 V On board regulators and jumpers allow the user to connect the CS43L22 s supplies to 1 8 V 2 5 V or 3 3 V for VL and 1 8 V or 2 5 V for VD VA and VA_HP All voltage inputs are referenced to ground using the black binding post J4 Stake headers J47 J52 J53 and J74 provide a convenient way to measure supply currents to the CS43L22 for VA_HP VL VD and VA supplies respe...

Page 5: ...ovides access to the serial audio signals required to interface with a DSP Figure 10 on page 20 The control port header provides bidirectional access to the I C control port signals by simply removing all the shunt jumpers from the USB position The user may then connect a ribbon cable connector to the Ext Sys Connect pins for external control of board functions A single row of GND pins are provide...

Page 6: ...The graphical user interface for the CDB43L22 Cirrus Logic Flex GUI allows the user to configure the CS43L22 registers and other component registers via the on board I C control bus The GUI interfaces with the CDB via the USB connection to a PC Section 4 Software Mode Control on page 11 provides a de scription of the Graphical User Interface GUI 1 11 USB Connector Connecting a USB port cable from ...

Page 7: ...criptions Provide S PDIF input to board via J61 or OPT3 PCM digital audio input can also be provided to the board via header J78 Shunt the left 2 pins on all rows of headers J8 and J109 Connect a ribbon cable to right 2 pins of all rows if external system connect is required Shunt left 2 pins of jumpers J16 J13 J20 J11 J17 J14 J23 and J12 Receive differential left and right channel PWM speaker out...

Page 8: ... to provide an actual headphone load while performance measurements are taken on HP jack J40 Digital S PDIF input can be provided on the optical OPT2 or RCA J68 jacks Jumpers J8 and J9 can be used to select output loads and jumpers J1 and J2 can be used to select filtered or unfiltered outputs Refer to Section 4 on page 11 for details on software configuration Figure 1 SPDIF In to Headphone or Lin...

Page 9: ...IF In to Stereo Speaker Out Table 2 shows the expected performance characteristics one should expect when using the CDB43L22 for SPDIF In to Stereo Speaker Out measurements Table 2 SPDIF In to Stereo Speaker Out Performance Plots Plot Location FFT S PDIF In to Speaker Out 0 dBFS Figure 25 on page 30 FFT S PDIF In to Speaker Out 60 dBFS Figure 26 on page 30 Frequency Response S PDIF In to Speaker O...

Page 10: ...is used to attach the mono differential channel to the measurement device Digital S PDIF input can be provided on the optical OPT2 or RCA J68 jacks Refer to Section 4 on page 11 for details on software configuration Figure 3 SPDIF In to Mono Speaker Out Table 3 shows the expected performance characteristics one should expect when using the CDB43L22 for SPDIF In to Mono Speaker Out measurements Tab...

Page 11: ... GUI by clicking on the Update button The default state of all registers are now visible For standard set up 6 Set up the signal routing in the Board Configuration tab as desired 7 Set up the CS43L22 in the Passthrough Power and Serial Audio Interface Configuration DSP Engine and Analog and PWM Output Volume tab as desired 8 Begin evaluating the CS43L22 For quick set up the CDB43L22 may alternativ...

Page 12: ...p is outlined below CS43L22 Basic Configuration Includes controls for configuring the interface format clocking functions and analog input signal routing in the CS43L22 See Section 4 2 through Section 4 4 for more controls in the CS43L22 CS8416 S PDIF Receiver Control Register controls for setting up the CS8416 Clock Source and Routing Selection Includes controls used to configure the value and so...

Page 13: ...n the setting of the associated control A description of each group is outlined below See the CS43L22 data sheet for complete register descriptions Power Control Register controls for powering down each section within the CS43L22 Analog Passthrough Configuration Controls for the input mixer summing amp and analog passthrough settings Serial Port Configuration Controls for all settings related to t...

Page 14: ...n the setting of the associated control A description of each control group is outlined below See the CS43L22 datasheet for complete register descriptions Digital Volume Control Digital volume controls and adjustments for the SDIN data and overall channel vol ume Mute gang invert and de emphasis functions are also available Limiter Configuration settings for the Limiter Tone Control Bass and trebl...

Page 15: ...elow the associated control This text will change depending on the setting of the associated control A description of each control group is outlined below See the CS43L22 datasheet for complete register descriptions Headphone Line Analog Output Volume controls and adjustments for the DAC channel outside of the DSP The modulation index and gain settings make up the parameters that determine the ful...

Page 16: ...can be modified bit wise or byte wise Left clicking on a particular register accesses that register and shows its contents at the bottom The user can change the register contents by using the push buttons by selecting a particular bit and typing in the new bit value or by selecting the reg ister in the map and typing in a new hex value Figure 8 Register Maps Tab CS43L22 ...

Page 17: ...nput Reload Xilinx program into the FPGA from Flash U14 H W BOARD RESET S1 Input Reset for the CS43L22 U1 AIN1 AIN2 J33 J37 Input Input 1 8 audio jacks for analog passthrough input signal to CS43L22 AIN3 AIN4 J45 J50 Input Input 1 8 audio jacks for Line or MIC analog passthrough input signals to CS43L22 A RC LPF B RC LPF J6 J18 Output Output 30 kHz LPF version of the signal on speaker binding post...

Page 18: ...es a filtered or a non filtered version of the SPKA signal to J99 1 2 SPKOUTB output routed to J99 2 3 SPKOUTB output not routed to J99 J15 MONO Applies a short between SPKOUT A and A Used only after MONO function is enabled in the CS43L22 OPEN Channel A and A to J59 and J60 respec tively SHUNTED Channel to J59 and J60 respectively J19 MONO Applies a short between SPKOUT B and B Used only after MO...

Page 19: ...e 9 Block Diagram USB µ controller CS43L22 S PDIF Input CS8416 PSIA Input Header FPGA Oscillator socket I2 C Interface Reset Reset PLL Clk Data SRC CS8421 Analog Output Line Headphone Speaker Outputs Analog Passthrough Input External System Input Header ...

Page 20: ...20 DS792DB1 CDB43L22 8 CDB43L22 SCHEMATICS Figure 10 CS43L22 Analog I O Schematic Sheet 1 ...

Page 21: ...DS792DB1 21 CDB43L22 Figure 11 S PDIF Digital Interface Schematic Sheet 2 ...

Page 22: ...22 DS792DB1 CDB43L22 Figure 12 Micro FPGA Control Schematic Sheet 3 ...

Page 23: ...DS792DB1 23 CDB43L22 Figure 13 Power Schematic Sheet 4 ...

Page 24: ...24 DS792DB1 CDB43L22 9 CDB43L22 LAYOUT Figure 14 Silk Screen CDB43L22 CS43L22 ...

Page 25: ...DS792DB1 25 CDB43L22 Figure 15 Top Side Layer ...

Page 26: ...26 DS792DB1 CDB43L22 Figure 16 GND Layer 2 ...

Page 27: ...DS792DB1 27 CDB43L22 Figure 17 Power Layer 3 ...

Page 28: ...28 DS792DB1 CDB43L22 Figure 18 Bottom Side Layer ...

Page 29: ...5 70 65 60 55 50 45 40 35 30 25 20 15 10 5 d B r A 10m 100m 20m 30m 40m 50m 60m 70m 80m 90m W 3 3 2 75 2 5 2 25 2 1 75 1 5 1 25 1 0 75 0 5 0 25 0 0 25 0 5 0 75 1 1 25 1 5 1 75 2 2 25 2 5 2 75 d B r A 20 20k 50 100 200 500 1k 2k 5k 10k Hz Figure 21 THD N vs HP Output Power Figure 22 Freq Resp S PDIF Input to HP Output 1 1430 Gain 1 000 0 8399 0 7099 0 6047 Note 2 100 40 97 5 95 92 5 90 87 5 85 82 5...

Page 30: ...2 5 2 1 5 1 0 5 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 d B r A 20 20k 50 100 200 500 1k 2k 5k 10k Hz 0 01 10 0 02 0 05 0 1 0 2 0 5 1 2 5 20 20k 50 100 200 500 1k 2k 5k 10k Hz Figure 27 Frequency Response S PDIF In to Speaker Out Figure 28 THD N S PDIF In to Speaker Out 0 01 10 0 02 0 05 0 1 0 2 0 5 1 2 5 200m 1 2 400m 600m 800m 1 W VP 3 7 V 0 01 10 0 02 0 05 0 1 0 2 0 5 1 2 5 0 2 200m 400m 600m 800m 1 1 2 ...

Page 31: ...y for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus This consent does not extend to other copying such as copying for general distribution advertising or promotional purposes or for creating any work for resale CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH PERSONAL INJURY OR SEVERE PROP ERTY OR ENVIRONME...

Page 32: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Cirrus Logic CDB43L22 ...

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