16
DS792DB1
CDB43L22
4.5
Register Maps Tab
The Register Maps tabs provide low-level control of the CS43L22, CS8416, CS8421, FPGA and GPIO reg-
ister settings. Register values can be modified bit-wise or byte-wise. “Left-clicking” on a particular register
accesses that register and shows its contents at the bottom. The user can change the register contents by
using the push-buttons, by selecting a particular bit and typing in the new bit value or by selecting the reg-
ister in the map and typing in a new hex value.
Figure 8. Register Maps Tab - CS43L22
Summary of Contents for CDB43L22
Page 20: ...20 DS792DB1 CDB43L22 8 CDB43L22 SCHEMATICS Figure 10 CS43L22 Analog I O Schematic Sheet 1 ...
Page 21: ...DS792DB1 21 CDB43L22 Figure 11 S PDIF Digital Interface Schematic Sheet 2 ...
Page 22: ...22 DS792DB1 CDB43L22 Figure 12 Micro FPGA Control Schematic Sheet 3 ...
Page 23: ...DS792DB1 23 CDB43L22 Figure 13 Power Schematic Sheet 4 ...
Page 24: ...24 DS792DB1 CDB43L22 9 CDB43L22 LAYOUT Figure 14 Silk Screen CDB43L22 CS43L22 ...
Page 25: ...DS792DB1 25 CDB43L22 Figure 15 Top Side Layer ...
Page 26: ...26 DS792DB1 CDB43L22 Figure 16 GND Layer 2 ...
Page 27: ...DS792DB1 27 CDB43L22 Figure 17 Power Layer 3 ...
Page 28: ...28 DS792DB1 CDB43L22 Figure 18 Bottom Side Layer ...
