12
DS792DB1
CDB43L22
4.1
Board Configuration Tab
The “Board Configuration” tab provides high-level control of signal routing on the CDB43L22. This tab also
includes basic controls that allow “quick setup” in a number of simple board configurations. Status text de-
tailing the CS43L22’s specific configuration appears directly below the associated control. This text may
change depending on the setting of the associated control. A description of each control group is outlined
below:
CS43L22 Basic Configuration
- Includes controls for configuring the interface format, clocking functions and
analog input signal routing in the CS43L22. See
for more controls in the
CS43L22.
CS8416 S/PDIF Receiver Control
- Register controls for setting up the CS8416.
Clock Source and Routing Selection
- Includes controls used to configure the value and source of the mas-
ter, frame and bit clocks which are sent to the CS43L22.
Update -
Reads all registers in the FPGA, CS43L22 and the CS8416 and shows the current values in the
GUI.
Reset
- Resets FPGA to default routing configuration.
Figure 4. Board Configuration Tab
Summary of Contents for CDB43L22
Page 20: ...20 DS792DB1 CDB43L22 8 CDB43L22 SCHEMATICS Figure 10 CS43L22 Analog I O Schematic Sheet 1 ...
Page 21: ...DS792DB1 21 CDB43L22 Figure 11 S PDIF Digital Interface Schematic Sheet 2 ...
Page 22: ...22 DS792DB1 CDB43L22 Figure 12 Micro FPGA Control Schematic Sheet 3 ...
Page 23: ...DS792DB1 23 CDB43L22 Figure 13 Power Schematic Sheet 4 ...
Page 24: ...24 DS792DB1 CDB43L22 9 CDB43L22 LAYOUT Figure 14 Silk Screen CDB43L22 CS43L22 ...
Page 25: ...DS792DB1 25 CDB43L22 Figure 15 Top Side Layer ...
Page 26: ...26 DS792DB1 CDB43L22 Figure 16 GND Layer 2 ...
Page 27: ...DS792DB1 27 CDB43L22 Figure 17 Power Layer 3 ...
Page 28: ...28 DS792DB1 CDB43L22 Figure 18 Bottom Side Layer ...
