Cinterion EGS5, Hardware Interface Description

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EGS5 Hardware Interface Description
3.3 Power Up / Power Down Scenarios
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EGS5_HD_v02.004 Page 34 of 123 2012-02-09
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3.3.2 Signal States after Startup
Table 8 describes the various states each interface signal passes through after startup and dur-
ing operation.
As shown in Figure 5 and Figure 6 signals are in an undefined state while the module is initial-
izing. Once the startup initialization has completed, i.e. when the software is running, all signals
are in defined state. The state of several signals will change again once the respective interface
is activated or configured by AT command:
Table 8:
Signal States
Signal name Undefined
state during
startup Defined state
after initialization Active state after configuration by AT
command
GPIO SPI I
2
C DAI
SYNC O, L O, L
CCIN I, PU I, PU
CCRST O, L O, L
CCIO O, L O, L
CCCLK O, L O, L
CCVCC O, L 2.9V
RXD0 I, PU O, H
TXD0 I, PU I, PD
CTS0 O, L O, L
1
RTS0 I, PU I, PD
DTR0 I, PU I, PU
DCD0 O, L O, H
DSR0 O, L O, L
1
RING0 I, PU O, H
2
RXD1 O, H O, H
TXD1 I, PD I, PD
CTS1 L O, L
1
RTS1 I, PD I, PD
SPIDI I Tristate I Tristate
SPICS I O, H O, L Tristate
I2CDAT_SPIDO I Tristate O, L/H IO
I2CCLK_SPICLK I Tristate O, L/H O, OD
GPIO1 I, PU Tristate IO
GPIO2 I, PU Tristate IO
GPIO3 I, PU Tristate IO
GPIO4 I, PD Tristate IO
GPIO5 O, L Tristate IO