Cinterion EGS5, Hardware Interface Description

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EGS5 Hardware Interface Description
Figures
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EGS5_HD_v02.004 Page 7 of 123 2012-02-09
Confidential / Released
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Figures
Figure 1: EGS5 system overview .................................................................................. 22
Figure 2: EGS5 block diagram ...................................................................................... 23
Figure 3: Power supply limits during transmit burst....................................................... 26
Figure 4: Position of the reference points BATT+ and GND ......................................... 27
Figure 5: Power-on with operating voltage at BATT+ applied before activating IGT .... 30
Figure 6: Power-on with IGT held low before switching on operating voltage
at BATT+........................................................................................................ 31
Figure 7: Timing of IGT if used as ON/OFF switch ....................................................... 32
Figure 8: Signal states during turn-off procedure .......................................................... 37
Figure 9: Battery pack circuit diagram .......................................................................... 43
Figure 10: Power saving and paging............................................................................... 48
Figure 11: Timing of CTSx signal (if CFUN= 7)............................................................... 49
Figure 12: Timing of RTSx signal (if CFUN = 9).............................................................. 49
Figure 13: RTC supply from capacitor............................................................................. 51
Figure 14: RTC supply from rechargeable battery .......................................................... 51
Figure 15: RTC supply from non-chargeable battery ...................................................... 51
Figure 16: Serial interface ASC0..................................................................................... 53
Figure 17: Serial interface ASC1..................................................................................... 55
Figure 18: USB circuit ..................................................................................................... 56
Figure 19: I
2
C interface connected to VCC of application ............................................... 57
Figure 20: I
2
C interface connected to VEXT line of EGS5 .............................................. 57
Figure 21: SPI interface................................................................................................... 58
Figure 22: Characteristics of SPI modes......................................................................... 59
Figure 23: Audio block diagram....................................................................................... 60
Figure 24: Single ended microphone input...................................................................... 62
Figure 25: Differential microphone input ......................................................................... 63
Figure 26: Line input configuration with OpAmp ............................................................. 64
Figure 27: Differential loudspeaker configuration............................................................ 65
Figure 28: Master PCM interface Application.................................................................. 67
Figure 29: Short Frame PCM timing................................................................................ 68
Figure 30: Long Frame PCM timing ................................................................................ 68
Figure 31: Slave PCM interface application .................................................................... 69
Figure 32: Slave PCM Timing, Short Frame selected ..................................................... 70
Figure 33: Slave PCM Timing, Long Frame selected...................................................... 70
Figure 34: Analog-to-Digital Converter (ADC)................................................................. 71
Figure 35: SYNC signal during transmit burst ................................................................. 73
Figure 36: LED Circuit (Example).................................................................................... 74
Figure 37: Incoming voice/fax/data call ........................................................................... 75
Figure 38: URC transmission .......................................................................................... 75
Figure 39: Antenna pads ................................................................................................. 76
Figure 40: 4 layer PCB stack for EGS5 interface board.................................................. 77
Figure 41: RF line on interface board. All dimensions are given in mm .......................... 79
Figure 42: Numbering plan for connecting pads (bottom view)....................................... 84
Figure 43: Audio programming model ............................................................................. 98
Figure 44: EGS5– top view ........................................................................................... 105
Figure 45: Dimensions of EGS5 (all dimensions in mm)............................................... 106
Figure 46: Land pattern (bottom view) .......................................................................... 107
Figure 47: Recommended stencil design (bottom view) ............................................... 108
Figure 48: Reflow Profile ............................................................................................... 109