Total Solution for Industrial Automation
12
CH 3. Data Memory
OFFSET
Item
Set-up value
parameter
Initial
value
Access
20
CH11 duty cycle ratio
Ex) When duty cycle ratio is set to 100, 100 x 0.1%
= 10.0%
0~1000
(x 0.1%)
0
R/W
21
CH12 duty cycle ratio
0~1000
0
R/W
22
Available Later
30
CH1 duty cycle ramp time(x10ms)
Ex) When Frequency ramp control time is set to 100,
100 x 10ms = 1,000ms (1sec)
0~65535
(x 10ms)
0
R/W
31
CH2 duty cycle ramp time(x10ms)
0~65535
0
R/W
32
CH3 duty cycle ramp time(x10ms)
0~65535
0
R/W
33
CH4 duty cycle ramp time(x10ms)
0~65535
0
R/W
34
CH5 duty cycle ramp time(x10ms)
0~65535
0
R/W
35
CH6 duty cycle ramp time(x10ms)
0~65535
0
R/W
36
CH7 duty cycle ramp time(x10ms)
0~65535
0
R/W
37
CH8 duty cycle ramp time(x10ms)
0~65535
0
R/W
38
CH9 duty cycle ramp time(x10ms)
0~65535
0
R/W
39
CH10 duty cycle ramp time(x10ms)
0~65535
0
R/W
40
CH11 duty cycle ramp time(x10ms)
0~65535
0
R/W
41
CH12 duty cycle ramp time(x10ms)
0~65535
0
R/W
…
Available Later
63
OS Version
0
R
…
Available Later
[Table 4] Usage and meaning of each buffer memory (PWM module)
※
R/W represents for the module’s Read/Write accesses from the CPU. (R: Read W:
Write)
※
All values in buffer memory will be erased and set to 0 when the power to the
CPU is turned off or stopped.
