User's Manual
18
Figure 3-4 Chipset Features Setup Screen
Item Help
Menu Level
DRAM Clock
DRAM Timing By SPD
SDRAM Cycle Length
Bank Interleave
Memory Hole
P2C/C2P Concurrency
Fast R-W Turn Around
System BIOS Cacheable
Video RAM Cacheable
Frame Buffer Size
AGP Aperture Size
AGP Fast Write
Flash BIOS Protection
OnChip Sound
OnChip Modem
CPU to PCI Write Buffer
PCI Dynamic Bursting
PCI Master 0 WS Write
PCI Delay Transaction
CMOS Setup Utility- Copyright (C) 1984-2001 Award Software
Advanced Chipset Features
:Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Fail-Safe Defaults F7:Optimized Defaults
Host CLK
Enabled
3
Disabled
Disabled
Enabled
Enabled
Disabled
Disabled
8M
64M
Disabled
Disabled
Auto
Auto
Enabled
Enabled
Enabled
Enabled
3-3 Advanced Chipset Features
By choosing the Advanced Chipset Features option from the CMOS Setup Utility
menu (Figure 3-1), the screen below is displayed. This sample screen contains the
manufacturer's default values for the mainboard
.
All of the above settings have been determined by the mainboard manufacturer
and should not be changed unless you are absolutely sure of what you are
doing. Explanation of the DRAM timing and chipset features setup is lengthy,
highly technical and beyond the scope of this manual. Below are abbreviated
descriptions of the functions in this setup menu. You can look on the world
wide web for helpful chipset and RAM configuration information including
AWARD's web site at http://www.award.com.
A. DRAM Timing By SPD
The function allows you to enable or disable the DRAM timing by SPD. When
Disabled, you can select the DRAM Clock, SDRAM Cycle Length and Bank
Interleave configuration.
B. SDRAM Cycle Length
When synchronous DRAM is installed, the number of the clock cycles of CAS
latency depends on the DRAM timing. Do not reset this setting from the default
value specified by the system designer.
