Casio UP-250, Technical Manual

Page: 53 / 165

24 X1 X1 I ---
Connected to ceramic vibration generator.
f=14.74 MHz ± 0.5%.
25 X2 X2 O --- Connected to ceramic. f=14.74 MHz ± 0.5%.
26 EA EA I TTL
External memory access. LOW: external ROM
HIGH: internal ROM (CPU mask).
27 P75 P75 (A16) O TTL External memory address A16 (software).
28 P76 P76 (A17) O TTL External memory address A17 (software).
29 P77 P77 (A18) O TTL External memory address A18 (software).
30 P80 WDTOUT O TTL
Watch dog timer error (and hardware limited
time power supply switch). LOW: error (reset).
31 P81/INT0 CLK IN/DTR I TTL Connected to pin #19.
32 P82 PF SW I TTL Paper feed switch. LOW: active.
33 ALE ALE O TTL
Address latch enable signal. Latches address
on bus AD0 to AD7 at fall.
34 VCC VCC I (+5 V) Main power terminal (+5 V).
35 AD AD0
3-state TTL
Address/data bus.
Transmits address (lower 8 bits) and data.
36 AD AD1
37 AD2 AD2
38 AD3 AD3
39 AD4 AD4
40 AD5 AD5
41 AD6 AD6
42 AD7 AD7
43 A8 A8
O TT LAddress bus (address upper 8 bits).
44 A9 A9
45 A10 A10
46 A11 A11
47 A12 A12
48 A13 A13
49 A14 A14
50 A15 A15
51 VSS VSS I (0 V) GND terminal.
52 P20 CR A/DSW1
I/O TTL
Carriage motor driver control 2-2 phase
excitation. All terminals on (LOW): hold.
DIP SW 1-1 to 1-4 read when P100, P101 are
LOW.
53 P21 CR B/DSW2
54 P22 CR C/DSW3
55 P23 CR D/DSW4
CPU pin functions
Pin
No. CPU
Function
Signal Name I/O Level Description
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