C&T Solution CT-CIB61, User Manual, Page: 36 / 76

CT-CIB61 Intel® 3rd Generation Core™ Processor i7/i5/i3 COM Express Type 6 Module
３６
(Offset G0x2C)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
GPIO0
(Offset G0x2E)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
GPIO4 GPIO3 GPIO2 GPIO1
Note:
Bit X = 0 means Polarity is retained
Bit X = 1 means Polarity is inverted
The GPIO4~GPIO7 can’t be set to inverted.
PSUEDO CODE 4.15.3
4.15.3.1 Example 1: Change GPIO2 from input to output
Step1: ByteData = ReadIOByte(0x506) //Read current setting from
configuration
//Register
Step2: ByteData = ByteData | 0xFD //Set Bit1 to 0. It means output
Step3: WriteIOByte(0x506, ByteData) //Write back to configuration register
4.15.3.2 Example2 Set GPIO7 to output LOW
Step1: ByteData = ReadIOByte(0x538) //Read current setting from Output Port
//Register
Step2: ByteData =ByteData & 0xEF //Set Bit4 to 0. It means output low
Step3: WriteIOByte(0x538, ByteData) //Write back to Output Port Register