C&T Solution CT-CIB61, User Manual, Page: 35 / 76

CT-CIB61 Intel® 3rd Generation Core™ Processor i7/i5/i3 COM Express Type 6 Module
３５
(Offset G0x04)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
GPIO0
(Offset G0x06)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
GPIO4 GPIO3 GPIO2 GPIO1
4.15.2.2.2 GPIO Input/Output Select Register 2
(Offset G0x34)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
GPIO7 GPIO6 GPIO5
Note:
Bit X = 0 means Output Pin
Bit X = 1 means Input Pin
4.15.2.3 GPIO Level for Input or Output
If Pin X configures as output pin, users can decide its output value (0 or 1).
If it is programmed as an input, this register reflects the state of the input
signal.
4.15.2.3.1 GPIO Level for Input or Output Register 1
(Offset G0x0C)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
GPIO0
(Offset G0x0E)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
GPIO4 GPIO3 GPIO2 GPIO1
4.15.2.3.2 GPIO Level for Input or Output Register 2
(Offset G0x38)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
GPIO7 GPIO6 GPIO5
4.15.2.4 GPIO Signal Invert Register
This will invert the polarity of the Input Port register data.