C&T Solution CT-CIB61, User Manual, Page: 34 / 76

CT-CIB61 Intel® 3rd Generation Core™ Processor i7/i5/i3 COM Express Type 6 Module
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Pin # GPIO# Default Configuration
A63 GPIO1 GPI1
A54 GPIO0 GPI0
The GPIO function, provided by Intel Panther IC, can be accessed through
GPIO Base Address Register (GPIOBASE). The configuration on CT-CIB61 is
described as below.
Register Address
GPIO Base Address 0x500
The general I/O read/write function is used to access and configure the
Panther Point. Through the I/O read or write command, the current status of
GPIO can configure each pin to input or output.
Registers Description 4.15.2
4.15.2.1 GPIO Use Select
4.15.2.1.1 GPIO Use Select Register 1
(Offset G0x00)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
GPIO0
(Offset G0x02)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
GPIO4 GPIO3 GPIO2 GPIO1
4.15.2.1.2 GPIO Use Select Register 2
(Offset G0x30)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
GPIO7 GPIO6 GPIO5
Note:
Bit X = 0 means Native Function
Bit X = 1 means GPIO Function
4.15.2.2 GPIO Input/Output Select
4.15.2.2.1 GPIO Input/Output Select Register 1