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13
PE_REFCLKp/n
I
PCIE 100MHz reference clock
4.3.3
CCLINK signal
CCLINK is an internal connection link between MLU290-M5 Intelligent Accelerating Cards.The
maximum transmission rate of CCLINK can be 50 Gbps PAM4, which is compatible with OAM specifications.
SERDE _[3
：
1]R/T[15:0],SERDE _5R/T[15:8] and SERDE _7R/T[7:0] are not used in MLU290-M5. The 48 pairs
of serdes in the table below are used
，
which are compatible with combine topology. For detailed internal
connection topology please refer to the reference topology chapter.
7Table 4.7 CCLINK Signal description
Signal
Direction of signal
Signal description
SERDES_4Tp/n [15:0]
O
CCLINK4[15:0] transmit signal
SERDES_4Rp/n [15:0]
I
CCLINK4[15:0] receiving signal
SERDES_5Tp/n [7:0]
O
CCLINK5[7:0] transmit signal
SERDES_5Rp/n [7:0]
I
CCLINK5[7:0] receiving signal
SERDES_6Tp/n [15:0]
O
CCLINK6[15:0] transmit signal
SERDES_6Rp/n [15:0]
I
CCLINK6[15:0] receiving signal
SERDES_7Tp/n [15:8]
O
CCLINK7[15:8] transmit signal
SERDES_7Rp/n [15:8]
I
CCLINK7[15:8] receiving signal
4.3.4
Other signals
4.3.4.1
SMBUS signal
I2C_SLV_D /CLK/ALERT# satisfy the SMBus protocol and supports 400KHz max, with 8 bit addresses
of 0x8E( write)/0x8F( read). MLU290-M5 works in slave mode.
8Table 4.8 SMBUS Signal description
Signal
Direction of signal
Signal description
I2C_SLV_D
I/O
I2C data signal
I2C_SLV_CLK
I
I2C clock signal
I2C_SLV_ALERT#
O
I2C alarm signal
SMBUS registers are described as follows:
