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Wiring!the!BITS!Timing!Interface!
The E7-20 supports synchronization to a local traceable network clock source via timing
inputs located on the E7-20 rear panel. Redundant closk (A and B) inputs are provided. The
E7-20 accepts a standard DSX-level timing source (DS1/T1 format only, not 64 kbps
composite clock format) and should be set to ESF/B8ZS. Wire the E7-20 timing inputs to a
Building Integrated Timing System (BITS) clock source using shielded cable.
Calix recommends providing traceable clock synchronization for E7-20 GPON applications
when T1/E1 Differential clock Recovery is required.
You can link up to ten collocated E7-20 shelves to share a BITS timing input. Calix offers a
connectorized daisy-chain BITS cable, or you can wire-wrap the individual daisy-chain links
between shelves.
To!wire!the!BITS!timing!input!interface!
1.!
Get up to two 24 AWG shielded 2-wire cables of sufficient length to reach the local
BITS clock interface from the E7-20. Use one cable to provide a single timing input (A
only), or two cables for a redundant input (A + B).
2.!
Strip approximately one inch of insulation from the wire ends.
3.!
Wire the E7-20 external timing input(s) as follows:
a.
!
Connect the timing wires to the E7-20 BITS
IN (A)
input position:
!
!
Wrap the positive (tip) wire to the
TIP+
pin.
!
!
Wrap the negative (ring) wire to the
RNG-
pin.
!
!
Wrap the cable shielding to the
SHLD
pin.
b.
!
To provide a redundant connection to the BITS clock source, repeat Step 3a to wire
the E7-20 BITS
IN (B)
input position, as required.
