Document type:
Title:
Revision date:
Revision:
User's Manual (MUT)
Mod. V793, ICARUS Slow Control Module
16/01/01
0
NPO:
Filename:
Number of
pages:
Page:
00100/98:V793x.MUTx/00
V793_REV0.DOC
19
6
1.3. Functional description
1.3.1. Baseline generation
The Mod. V793 generates two DC voltage levels (DAC1 and DAC2) which allows to set the
baseline acquisition for the V791 boards; the DC levels can be remotely programmed with
12 bit resolution on the 0
÷
+2.5 V range either via RS232 or CAENET interface. For each
V791 board, it is possible to select the baseline (DAC1 or DAC2) according to the type of
signal to be converted by acting on a backplane jumper.
1.3.2. EN_BRD signals generation
The Mod. V793 is able to generate the EN_BOARD[1…19] TTL signals which allow to
enable/disable each of the V791 boards within an analog crate. If the EN_BOARD[n] signal
is active, the n-th V791 board is forced into reset state and signal digitisation is stopped.
The EN_BOARD signals can be remotely programmed either via RS232 or CAENET
interface.
1.3.3. Clock signal generation
The Mod. V793 houses a 40 MHz quartz oscillator producing an LVDS differential clock
signal CLOCK+/CLOCK-; this signal is employed to synchronise data acquisition on all the
V791 modules in a crate. The clock signal can be also externally supplied via the front
panel CLK I/O connector. The internal/external clock selection is performed through the
JP8 jumpers (see § 2.6 for further details)
1.3.4. Detector and crate power supply voltages measurement
The Mod. V793 houses eight 8-bit ADCs dedicated to detector and crate power supply
voltages measurement on the relevant backplane lines (see table below). The ADCs can be
read out either via RS232 or CAENET interface.
Line
Range
Line
Range
CON_HV1
±
2.5 V
GND
±
0.5 V
CON_HV2
±
2.5 V
+5 V
5
±
1 V
CON_HV3
±
2.5 V
+5 V ANALOG
5
±
1 V
CON_HV4
±
2.5 V
-5 V ANALOG
-5
±
1 V
