Document type:
Title:
Revision date:
Revision:
User's Manual (MUT)
Mod. V793, ICARUS Slow Control Module
16/01/01
0
NPO:
Filename:
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pages:
Page:
00100/98:V793x.MUTx/00
V793_REV0.DOC
19
13
2.6. Jumpers
Please refer to Fig. 2.3 for jumpers location.
J8:
CLK input termination
•
Jumper between pin 2 and 3
⇒
termination ON
•
Jumper between pin 1 and 2
⇒
termination OFF
JP3:
clock configuration
•
Jumper between pin 3 and 4
⇒
the internal oscillator drives the CK+/CK- backplane
lines
•
Jumper between pin 5 and 6
⇒
the external clock signal is sent to the CK+/CK-
backplane lines
These two settings are mutually exclusive.
•
Jumper between pin 1 and 2
⇒
the internal oscillator drives the front panel CLK output
•
Jumper between pin 2 and 4
⇒
the clock signal on the CK+/CK- backplane lines is
sent to the front panel CLK output.
These two settings are mutually exclusive.
JP1:
RS232 port configuration
Two jumpers allow to exchange the TX and RX pins (see Fig. 2.4) according to the cable to
be used.
JP3
5
3
1
6
4
2
J P 1
3
1
4
2
J8
3
2
1
Fig. 2.3 - Jumpers location
