CAEN
Electronic Instrumentation
UM5175
–
V2495/VX2495 User Manual rev. 1
46
The UFPGA can set the relevant configuration registers and read data from the generator through the SPI protocol.
CAEN does not provide a detailed description of the communication protocol over the SPI bus for GDG configuration. A
VHDL component is provided in the gd_control.vhd source code (GD_CONTROL), included in all the user demo
firmware.
GD_CONTROL implements the following registers that can be accessed from the local bus. The LB_INT component
reserves addresses starting from 0x7F00 to GD_CONTROL access. LB_INT and GD_CONTROL are connected by a
dedicated interface for register write and read.
A set of LB registers are used to configure the GDG, as described in
ADDRESS
REGISTER/CONTENT
ACCESS MODE
Read/Write
Base + 0x7F00
Base + 0x7F04
Base + 0x7F08
Base + 0x7F0C
Base + 0x7F10
Data Write
Command register
Control register
Data read
Status register
A24/A32
A24/A32
A24/A32
A24/A32
A24/A32
D16/D32
D16/D32
D16/D32
D16/D32
D16/D32
R
R
R
R
R
Tab. 10.10:
Local Bus registers description for the Gate and Delay Generator configuration
Register Description
➢
DATA WRITE:
the datum (gate or delay) must be written here before it is transmitted through SPI to the GDG.
Address:
0x7F00.
Mode:
Read only.
Bit
Description
[31:0]
Gate or delay datum to transmit to the GDG
➢
COMMAND register:
it is where the action to be performed is set. The action depends on the value of the 2 LSBs of
the Control register (read or write mode): one of these bits should be asserted to execute the related action. The
channel interested by the action is set through the 6 LSBs of the register (relevant when [15:0] = 0x100 in write
mode and [15:0] = 0x2000, 0x3000 in read mode).
Address:
0x7F04
Mode:
Read only
Write Mode
Bit
Description
[31:16]
reserved
[15:0]
0x2000 = the internal gate value is modified with the content of the data write register (but
not sent to the DFPGA)
0x3000 = the internal delay value is modified with the content of the data write register (but
not sent to the DFPGA)
channel) = the gate AND delay values of the selected channel are modified with the
internal values, sent to the DFPGA by the UFPGA through SPI
0x0300 = the delay of all channels is reset
0x0400 = the delay of all channels is calibrated
0x0500 = the internal gate and delay values are broadcast to all 32 channels
Read Mode
Bit
Description
[31:16]
reserved
[15:0]
channel) = the gate value of the specified channel is read through SPI
channel) = the delay value of the specified channel is read through SPI
