Trigger coincidence level
Opera ng the waveform recording firmware, the acquisi on trigger is common to the whole board. This
common trigger allows the coincidence acquisi on mode to be performed through the Majority opera on.
Enabling the coincidences is possible by wri ng at register address 0x810C
:
• Bits[3:0] enable a specific channel self-trigger to par cipate in the coincidence;
• Bits[23:20] set the coincidence window (T
TVAW
) linearly in steps of the Trigger clock (10 ns);
• Bits[26:24] set the Majority (i.e. Coincidence) level; the coincidence takes place when:
Number of enabled channels > Majority level
Supposing that bits[3:0] = F (i.e. all channels are enabled) and bits[26:24] = 01 (i.e. Majority level = 1), a
common trigger is issued whenever at least two of the enabled self-triggers are in coincidence within the
programmed T
TVAW
.
The Majority level must be smaller than the number of channels enabled via bits[3:0] mask. By default,
bits[26:24] = 00 (i.e. Majority level = 0), which means the coincidence acquisi on mode is disabled and the
T
TVAW
is meaningless. In this case, the common trigger is simple OR of the enabled channel self-triggers.
Note
: in order not to overload the plots but preserve the clearness of concept, only CH0 and CH1 are
supposed to be fed with input pulses in the following figures.
Fig.
shows the trigger management in case the coincidences are disabled.
CH1 THRESHOLD
CH0(enabled) IN
CH0 THRESHOLD
TRIGGER
(Maj.lev = 0)
CH1(enabled) IN
OR signal
SELF-TRG[CH0]
SELF-TRG[CH0]
Fig. 7.15:
Self-trigger rela onship with Majority level = 0.
Fig.
shows the trigger management in case the coincidences are enabled with Majority level = 1 and
T
TVAW
is a value different from 0.
Note
: with respect to the posi on where the common trigger is generated, the por on of input signal
stored depends on the programmed length of the acquisi on window and on the post trigger se ng.
40
UM3247 - N6724 User Manual rev. 10
