Caen N6724, User Manual

Page: 27 / 61

Event structure
The event can be readout via USB or Op cal Link; data format is 32-bit long word (see Fig. 7.4 ).
An event is structured as:
• Header (four 32-bit words)
• Data (variable size and format)
Header
The Header consists of four words including the following informa on:
• EVENT SIZE (bits[27:0] of 1
st
header word) is the total size of the event, i.e. the number of 32-bit long
words to be read.
• BOARD FAIL FLAG (bit[26] of 2
nd
header word) implemented from ROC FPGA firmware revision 4.5 on
(reserved otherwise), it is set to “1” in consequence of a hardware problem (e.g. PLL unlocking). The
user can collect more informa on about the cause by reading at register address 0x8104 and contact
CAEN Support Service if necessary (see Chap.
Technical Support ).
• ZLE FLAG (bit[24] of 2
nd
header word) indicates whether the ZLE suppression mode is enabled (1) or
not (0) (see Sec. Zero Length Encoding ZLE ).
• TRG OPTIONS (bits[23:8] of 2
nd
header word); star ng from revision 4.6 of the ROC FPGA firmware
(reserved otherwise), these 16 bits can be programmed to provide trigger informa on according to
the se ng of the bits[22:21] at register address 0x811C (see Tab
7.2 ).
REGISTER 0x811C
Bits[22:21]
FUNCTIONAL
DESCRIPTION
Reserved /TRG OPTIONS INFORMATION
(16 bits in the
2
nd
header word)
00
(default)
Reserved Must be 0 .
01 Event Trigger Source
Indicates the trigger source causing the
event acquisi on:
Bits[23:19] = 00000
Bit[18] = So ware Trigger
Bit[17] = External Trigger
Bit[16:12] = 000000
Bits[11:8] = Channel self-trigger (refer to
Sec.
Self-Trigger ).
10
Extended Trigger Time Tag
(ETTT)
A 48-bit Trigger Time Tag (ETTT) informa-
on is configured, where Bits[23:8] con-
tributes as the 16 most significant bits to-
gether to the 32-bit TTT field (4
th
header
word).
Note : in the ETTT op on, the overflow bit
is not provided.
11 Not used If configured, it acts like “00” se ng.
Tab. 7.2: Reserved/Trg Op ons configura on table.
• CHANNEL MASK (bits[3:0] of 2
nd
header word) is the mask of the channels par cipa ng in the event
(e.g. CH0 and CH2 par cipa ng → Channel Mask = 0x3). This informa on must be used by the so -
ware to acknowledge from which channel the samples are coming (the first event contains the sam-
ples from the channel with the lowest number).
• EVENT COUNTER (bits[23:0] of 3
rd
header word) is the trigger counter; it can count either accepted
triggers only, or all triggers (bit[3] of register address 0x8100).
UM3247 - N6724 User Manual rev. 10 27