Document type:
Title:
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Revision:
User's Manual (MUT)
Mod. DT5740 32 Channel 12bit - 65MS/s Digitizer
04/05/2016
12
NPO:
Filename:
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00100/09:5740x.MUTx/12
DT5740_REV12.DOC
50
36
3.5
Reset, Clear and Default Configuration
3.5.1
Global Reset
Global Reset is performed at Power-On of the module or via software by write access at register
address 0xEF24 (whatever 32-bit value can be written). It allows to clear the data off the Output
Buffer, the event counter and performs a FPGAs global reset, which restores the FPGAs to the
default configuration. It initializes all counters to their initial state and clears all detected error
conditions.
3.5.2
Memory Reset
The Memory Reset clears the data off the Output Buffer.
The Memory Reset can be forwarded via either a write access at register address 0xEF28
(whatever 32-bit value can be written).
3.5.3
Timer Reset
The Timer Reset allows to initialize the timer which allows to tag an event. The Timer Reset can
be forwarded with a pulse sent to the front panel GPI input (leading edge sensitive).
