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User's Manual (MUT)
Mod. DT5740 32 Channel 12bit - 65MS/s Digitizer
04/05/2016
12
NPO:
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00100/09:5740x.MUTx/12
DT5740_REV12.DOC
50
30
3.4.1
Software Trigger
Software triggers are internally produced via a software command (write access at register
address 0x8108) through USB or Optical Link.
3.4.2
External Trigger
A TTL or NIM external signal can be provided to the front panel TRG-IN connector (configurable
at register address 0x811C). If the external trigger is not synchronized with the internal clock, a 1-
clock period jitter occurs.
3.4.3
Self-Trigger
In the trigger domain, the input channels of the DT5740 are managed as 8-channel groups:
Group 0 = 0÷7 Ch, Group 1 = 8÷15 Ch, Group 2 = 16÷23 Ch and Group 3 = 24 ÷31 Ch. Each
channel in a group (GRx_CHy_IN) is able to generate a self-trigger signal (SELF_TRG) when the
digitized input pulse goes over or under a configurable threshold, according to bit[6] of register
address 0x8000 (see Fig. 3.6). The threshold, common to each group, is set is set through the
register address 0x1n80 (n is the group number). The self-triggers of each group are ORed to
generate a trigger request (TRG_REQ). The trigger requests are then propagated to the central
trigger logic where they are ORed to produce the board common trigger, which is finally
distributed back to all channels in the groups causing the event acquisition (see Fig. 3.5).
GRx_CHy_IN
THRESHOLD
Overthreshold signal from
channel x in group y
Underthreshold signal from
channel x in group y
(
Group Configuration
register bit[6] =0)
(
Group Configuration
register bit[6] =1)
Fig. 3.6: Self-trigger generation
The FPGA, through the address 0x1nA8, can be programmed to decide which channels in the
group do participate in the trigger request generation.
Besides, the FPGA, through the address 0x810C can be programmed to enable those groups
participating in the board common trigger generation.
