Cactus Technologies, Limited
4.1.8.
Drive/Head (LBA 27-24) Register
The Drive/Head register is used to select the drive and head. It is also used to select LBA
addressing instead of cylinder/head/sector addressing. The bits are defined as follows:
D7
D6
D5
D4
D3
D2
D1
D0
1
LBA
1
DRV
HS3
HS2
HS1
HS0
Bit 7
This bit is set to 1.
Bit 6
LBA is a flag to select either Cylinder/Head/Sector (CHS) or Logical Block Address Mode (LBA).
When LBA=0, Cylinder/Head/Sector mode is selected. When LBA=1, Logical Block Address is
selected. In Logical Block Mode, the Logical Block Address is interpreted as follows:
LBA07-LBA00: Sector Number Register D7-D0.
LBA15-LBA08: Cylinder Low Register D7-D0.
LBA23-LBA16: Cylinder High Register D7-D0.
LBA27-LBA24: Drive/Head Register bits HS3-HS0.
Bit 5
This bit is set to 1.
Bit 4 (DRV)
DRV is the drive number. This should always be set to 0.
Bit 3 (HS3)
When operating in the Cylinder, Head, Sector mode, this is bit 3 of the head number. It
is Bit 27 in the Logical Block Address mode.
Bit 2 (HS2)
When operating in the Cylinder, Head, Sector mode, this is bit 2 of the head number. It
is Bit 26 in the Logical Block Address mode.
Bit 1 (HS1)
When operating in the Cylinder, Head, Sector mode, this is bit 1 of the head number. It
is Bit 25 in the Logical Block Address mode.
Bit 0 (HS0)
When operating in the Cylinder, Head, Sector mode, this is bit 0 of the head number. It
is Bit 24 in the Logical Block Address mode.
4.1.9.
Status Registers
These registers return the status when read by the host. Reading the Status register does
clear a pending interrupt while reading the Auxiliary Status register does not. The meaning
of the status bits are described as follows:
D7
D6
D5
D4
D3
D2
D1
D0
BUSY
RDY
DWF
DSC
DRQ
CORR
0
ERR
Bit 7 (BUSY)
The busy bit is set when the device has access to the command buffer and registers
and the host is locked out from accessing the command register and buffer. No other
bits in this register are valid when this bit is set to a 1.
Bit 6 (RDY)
RDY indicates whether the device is capable of performing operations requested by the
host. This bit is cleared at power up and remains cleared until the device is ready to
accept a command.
Bit 5 (DWF)
This bit, if set, indicates a write fault has occurred.
Bit 4 (DSC)
This bit is set when the device is ready.
Bit 3 (DRQ)
The Data Request is set when the device requires that information be transferred
either to or from the host through the Data register.
Bit 2 (CORR)
This bit is set when a Correctable data error has been encountered and the data has
been corrected. This condition does not terminate a multi-sector read operation.
Bit 1 (IDX)
This bit is always set to 0.
Bit 0 (ERR)
This bit is set when the previous command has ended in some type of error. The bits in
the Error register contain additional information describing the error.
Cactus Technologies Limited
Industrial Grade -910S/910S-P1 Series SSD Product Manual
v2.2
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