Cactus Technologies, Limited
4.1.1.
Data Register
The Data Register is a 16-bit register, and it is used to transfer data blocks between the SSD
data buffer and the Host.
4.1.2.
Error Register
This register contains additional information about the source of an error when an error is
indicated in bit 0 of the Status register. The bits are defined as follows:
D7
D6
D5
D4
D3
D2
D1
D0
BBK
UNC
0
IDNF
0
ABRT
0
AMNF
Bit 7 (BBK)
This bit is set when a Bad Block is detected.
Bit 6 (UNC)
This bit is set when an Uncorrectable Error is encountered.
Bit 5
This bit is 0.
Bit 4 (IDNF)
The requested sector ID is in error or cannot be found.
Bit 3
This bit is 0.
Bit 2 (Abort)
This bit is set if the command has been aborted because of a status condition: (Not
Ready, Write Fault, etc.) or when an invalid command has been issued.
Bit 1
This bit is 0.
Bit 0 (AMNF)
This bit is set in case of a general error.
4.1.3.
Feature Register
This register provides information regarding features of the SSD that the host can utilize.
4.1.4.
Sector Count Register
This register contains the number of sectors of data requested to be transferred on a read or
write operation between the host and the SSD. If the value in this register is zero, a count of
256 sectors is specified. If the command was successful, this register is zero at command
completion. If not successfully completed, the register contains the number of sectors that
need to be transferred in order to complete the request.
4.1.5.
Sector Number (LBA 7-0) Register
This register contains the starting sector number or bits 7-0 of the Logical Block Address
(LBA) for any SSD data access for the subsequent command.
4.1.6.
Cylinder Low (LBA 15-8) Register
This register contains the low order 8 bits of the starting cylinder address or bits 15-8 of the
Logical Block Address.
Cactus Technologies Limited
Commercial Grade -250SH Series SSD Product Manual
v2.1
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