CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
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Rev.1.7
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2. Bit [0]: When SPI interface is master mode, SPI interrupt happened when bit [0] ==1 and every SPI master command
completed. Interrupt (HID) would be cleaned once address 0x10 was written.
6.9.5
SPI Control Register 3
Address: 3fh
Bits
R/W
Bit Mnemonic
Description
default
7-0
R/W
data_len
The data length of read/write,
0000_0000: Reserved
0000_0001: 1 bytes
0000_0010: 2 bytes
0000_0011: 3 bytes
.
.
.
1111_1111:255 bytes
8’d0
(POR)
SPI example for master mode:
Write 3 bytes:
(Address = 92, DATA = 55,AA)
Write 0x38~0x3A = 92 55 AA (Data register)
Write 0x3F = 03 (Write 3 bytes length)
Write 0x3D = A0 (SPI start)
Read 3 bytes:
(Address = 92)
Write 0x38= 92 (Data register)
Write 0x3F = 03 (Read 3 bytes length)
Write 0x3D = 80 (SPI start)
Read 0x38~0x3A
