C-Media CM6533 Manual Download Page 7

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CM6533,CM6533N,CM6533X1,CM6533DH

USB Audio Chip

Page

www.cmedia.com.tw

Rev.1.7



Single 5V power supply (embedded 5V to 1.8V regulator for digital core, 5V to 3.3V regulator for digital IO, 5V to

3.6V regulator for analog codec)



3.3V digital I/O pads with 5V tolerance



Industrial standard LQFP-48 package (7x7mm)

2.5

Audio I/O



Playback Stream:



Speaker/Headphone



Sample Rates: 8K/11.025K/16K/22.05K/32K/44.1K/48K/88.2K/96KHz



Supports Bit Length: 16/24bits



Speaker Gain Range (Analog) is -44 ~ 0dB, 1dB/step



DAC Gain Range (Digital) is -62 ~ 0dB, 1dB/step



S/PDIF transmitter



Sample Rates: 44.1K/48K/88.2K/96KHz



Supports Bit Length: 16/24 bits



Recording Stream:



Microphone



Sample Rates: 8K/11.025K/16K/22.05K/32K/44.1K/48K/88.2k/96KHz



Supports Bit Length: 16/24 bits



Microphone gain range (Analog) is -18 ~ 45dB, 1dB/step



ADC gain range (Digital) is -16 ~ 12dB, 1dB/step



Stereo Mixer



Mix stereo playback stream and stereo microphone



Stereo Mixer gain range is -30 ~ 33dB, 1dB/step



A-A path Stream:



Microphone to playback A-A path



Mix mono microphone input to stereo playback both L/R channel



The Microphone A-A path gain range is -15 ~ 32dB, 1dB/step

**Note 1: A-A path means Analog to Analog Mixer path

**Note 2:

CM6533/CM6533N/CM6533X1/CM6533DH is a USB 2.0 Full Speed audio device. Since bandwidth limitation,

CM6533/CM6533N/CM6533X1/CM6533DH cannot support 96KHz/24bits for playback and capture streams

simultaneously. The possible combinations are shown below:

Playback

Capture

Audio Format

Stereo, 96KHz/24bits

Stereo, 48kHz/24bits or below

Mono, 96KHz/24bits or below

Stereo, 48kHz/24bits or below

96KHz/24bits

Mono, 96KHz/24bits or below

Summary of Contents for CM6533

Page 1: ...96 KHz sampling rate and 16 24 bits resolution The CM6533 CM6533N CM6533X1 CM6533DH integrates equalizer on both playback and recording paths to compensate the frequency response of microphone and headphone The CM6533 CM6533N CM6533X1 CM6533DH also integrates 256K Byte flash Including 32KB F W programming size and crystal but requires few passive components to make a finish product Thus it can sav...

Page 2: ...6533X1 CM6533DH Pin out diagram 5 Modify flash description 256K Byte flash Including 32KB F W programming size 1 4 2015 3 30 1 Remove Microphone input impedance chart 2 Add Xear and Dolby software function descriptions CH7 CH8 3 Modify Operating ambient temperature to 15 70 o C 4 Modify CH5 1 CH5 2 USB Topology chart 5 Modify Block Diagram Page1 6 Add Cap less cross talk performance 7 Add CM6533N ...

Page 3: ... 4 2 CM6533N Pin out Diagram QFN48 11 4 3 CM6533X1 Pin out Diagram LQFP48 12 4 4 CM6533DH Pin out Diagram LQFP48 13 4 5 Pin Description 14 4 6 Pin Circuit Diagrams 17 5 USB Audio Topology 18 5 1 CM6533N CM6533 Headset Topology 18 5 2 CM6533X1 CM6533DH Headset Topology 19 6 Function Description 20 6 1 Playback Equalizer 20 6 1 1 5 band equalizer 20 6 1 2 Four 4 Preset EQ Mode 22 6 2 Recording Equal...

Page 4: ...nd Status Register 36 6 8 10 I2C Master Clock Period Setting Register 37 6 8 11 I2C Slave Mode 38 6 8 12 I2C Slave Data Register 38 6 8 13 I2C Slave Status Register 38 6 8 14 I2C Slave Memory Address Pointer MAP Register 39 6 8 15 I2C Slave Status Register 39 6 9 SPI Interface 41 6 9 1 SPI Registers Descriptions 41 6 9 2 SPI Control Register 0 41 6 9 3 SPI Control Register 1 42 6 9 4 SPI Interrupt...

Page 5: ...olby Headphone v2 51 8 2 Dolby Pro Logic IIx 51 8 3 Xear Environment Effect 51 8 4 Xear Software 10 Band Equalizer 51 8 5 Xear Magic Voice 51 9 Electrical Characteristics 52 9 1 Absolute Maximum Ratings 52 9 2 Recommended Operation Conditions 52 9 3 Power Consumption 52 9 4 DC Characteristics 52 9 5 Analog Audio 53 9 6 USB Transceiver 53 9 7 Microphone Bias 53 10 Audio Performance 54 10 1 DAC Audi...

Page 6: ...microphone and headphone The CM6533 CM6533N CM6533X1 CM6533DH also integrates 256K Byte flash Including 32KB F W programming size and crystal but requires few passive components to make a finish product Thus it can save the total BOM cost and PCB area can be smaller 2 Features 2 1 USB Compliance USB 2 0 Full Speed compliant USB Audio Class 1 0 compliant USB Human Interface Device HID Class 1 1 com...

Page 7: ...6K 22 05K 32K 44 1K 48K 88 2k 96KHz Supports Bit Length 16 24 bits Microphone gain range Analog is 18 45dB 1dB step ADC gain range Digital is 16 12dB 1dB step Stereo Mixer Mix stereo playback stream and stereo microphone Stereo Mixer gain range is 30 33dB 1dB step A A path Stream Microphone to playback A A path Mix mono microphone input to stereo playback both L R channel The Microphone A A path g...

Page 8: ...533DH Compared Table The pin out of CM6533 CM6533N CM6533X1 and CM6533DH are all the same and they only differ in firmware software and package CM6533N CM6533 CM6533X1 CM6533DH Package QFN48 LQFP48 LQFP48 LQFP48 Firmware Optional Jack Detection Optional Jack Detection Software Jack Detection Xear Surround HP Dolby Headphone For the detailed firmware and software information please refer to its cor...

Page 9: ... Audio Chip Page 9 60 www cmedia com tw Rev 1 7 Copyright C Media Electronics Inc 3 Applications USB Headset Gaming Headset Microsoft Lync Skype VoIP Headset Notebook Netbook Docking Android Phone Slate Docking USB Speaker USB Microphone ...

Page 10: ...21 22 23 24 48 47 46 45 42 43 44 39 40 41 37 38 36 25 32 33 34 35 26 27 28 29 30 31 LOCOM LOUTR MIC_SWOUT VOLADJ AGND MBIASL LOUTL DVDD18 DVDD50 USB_DM USB_DP VSS DVDD33 SPDIF_O TEST PDSW GPIO_0 GPIO_1 I2C_SCLK GPIO_2 I2C_SDAT SPI_MISO GPIO_6 GPIO_7 GPIO_3 GPIO_4 GPIO_5 GPIO_8 GPIO_10 GPIO_9 GPIO_11 MICL MICR_RING2 SPI_MOSI SPI_CS0 SPI_SCK VSS MBIASR_SLEEVE AGND AVDD36 AVDD50 AV42_DA VAG VSS AV36_...

Page 11: ... 24 48 47 46 45 42 43 44 39 40 41 37 38 36 25 32 33 34 35 26 27 28 29 30 31 LOCOM LOUTR MIC_SWOUT VOLADJ AGND MBIASL LOUTL DVDD18 DVDD50 USB_DM USB_DP VSS DVDD33 SPDIF_O TEST PDSW GPIO_0 GPIO_1 I2C_SCLK GPIO_2 I2C_SDAT SPI_MISO GPIO_6 GPIO_7 GPIO_3 GPIO_4 GPIO_5 GPIO_8 GPIO_10 GPIO_9 GPIO_11 MICL MICR_RING2 SPI_MOSI SPI_CS0 SPI_SCK VSS MBIASR_SLEEVE AGND AVDD36 AVDD50 AV42_DA VAG VSS AV36_DAR AGND...

Page 12: ...3 24 48 47 46 45 42 43 44 39 40 41 37 38 36 25 32 33 34 35 26 27 28 29 30 31 LOCOM LOUTR MIC_SWOUT VOLADJ AGND MBIASL LOUTL DVDD18 DVDD50 USB_DM USB_DP VSS DVDD33 SPDIF_O TEST PDSW GPIO_0 GPIO_1 I2C_SCLK GPIO_2 I2C_SDAT SPI_MISO GPIO_6 GPIO_7 GPIO_3 GPIO_4 GPIO_5 GPIO_8 GPIO_10 GPIO_9 GPIO_11 MICL MICR_RING2 SPI_MOSI SPI_CS0 SPI_SCK VSS MBIASR_SLEEVE AGND AVDD36 AVDD50 AV42_DA VAG VSS AV36_DAR AGN...

Page 13: ...3 24 48 47 46 45 42 43 44 39 40 41 37 38 36 25 32 33 34 35 26 27 28 29 30 31 LOCOM LOUTR MIC_SWOUT VOLADJ AGND MBIASL LOUTL DVDD18 DVDD50 USB_DM USB_DP VSS DVDD33 SPDIF_O TEST PDSW GPIO_0 GPIO_1 I2C_SCLK GPIO_2 I2C_SDAT SPI_MISO GPIO_6 GPIO_7 GPIO_3 GPIO_4 GPIO_5 GPIO_8 GPIO_10 GPIO_9 GPIO_11 MICL MICR_RING2 SPI_MOSI SPI_CS0 SPI_SCK VSS MBIASR_SLEEVE AGND AVDD36 AVDD50 AV42_DA VAG VSS AV36_DAR AGN...

Page 14: ...ack type and switch to MICR_RING2 or MBIASR_SLEEVE 15 MICL AI Microphone in left channel 19 MICR_RING2 AI Microphone in right channel or combo jack Ring2 pin input 16 MBIASL AO Microphone bias 2 75V for Left channel 20 MBIASR_SLEEVE AO Microphone bias 2 75V for Right channel or combo jack Sleeve pin input 17 VAG AO Voltage reference cap filter 26 LOUTL AO Line out left channel 28 LOCOM AO Line out...

Page 15: ...n enable via configuration tool or firmware 35 GPIO_8 DIO General purpose input output 3 3V I O 5V tolerance bidirectional buffer with 8mA driving current Default EQ disable and weak pull up for input 34 GPIO_9 DIO General purpose input output default Rec Clip Indicator 3 3V I O 5V tolerance bidirectional buffer with 8mA driving current Default weak pull up for input 33 GPIO_10 DIO Programmable 3 ...

Page 16: ...rmal mode 0 Suspend mode 1 3 TEST DI The TEST pin is used for IC test another one is in the situation when F W was crash or USB was not recognized Set TEST pin to 3 3V before USB connect can force MCU into boot loader mode and able to update F W via configuration tool Default weak pull down for input 1 Boot loader mode 0 Normal operation Note1 GPIOs I2C SPI SPDIF MIC_SWOUT MICL MICR_RING2 MBIASL M...

Page 17: ...udio Chip Page 17 60 www cmedia com tw Rev 1 7 Copyright C Media Electronics Inc 4 6 Pin Circuit Diagrams VAG MIC_BAIS AGND VAG VSS Analog input pins LINE MIC ADC AGND Output pins LOUTL LOUTR AGND LOUT_n Output pins LOUTL LOUTR VREG VDD VSS ...

Page 18: ...ce Description Endpoint Interface 0 Audio Control Interface Interface 1 Audio Stream Interface for Playback 0x01 Interface 2 Audio Stream Interface for Record 0x82 Interface 3 HID Interface 0x87 Interrupt In 16 bytes Audio Stream Interfaces Alternate Setting List Interface 1 Speaker Alt 1 2CH 16Bits PCM 8K 11 025K 16K 22 05K 32K 44 1K 48K Alt 2 2CH 24Bits PCM 8K 11 025K 16K 22 05K 32K 44 1K 48K Al...

Page 19: ...Interface 0 Audio Control Interface Interface 1 Audio Stream Interface for Playback 0x01 Interface 2 Audio Stream Interface for Record 0x82 Interface 3 HID Interface 0x87 Interrupt In 16 bytes Audio Stream Interfaces Alternate Setting List Interface 1 Speaker Alt 1 2CH 16Bits PCM 8K 11 025K 16K 22 05K 32K 44 1K 48K Alt 2 2CH 24Bits PCM 8K 11 025K 16K 22 05K 32K 44 1K 48K Alt 3 2CH 16Bits PCM 88 2K...

Page 20: ...ficients such as center frequency gain values and bandwidth to one optimized frequency response curve and setting in terms of the headphone driver and housing s acoustics characteristics also via embedded FLASH programming The EQ engine contains five 5 frequency bands Fc of digital filters to conduct transfer functions of the frequency response over the audio band It allows maximum 12dB digital ga...

Page 21: ...Q setting and could not allow users to dynamically change into different preset modes Clients could also consider reporting Treble Bass feature unit by embedded FLASH to Windows UAA driver to allow end users to adjust Bass F1 and Treble F5 by themselves Therefore there are three usage application scenarios as shown by the summary table below 3 EQ Usage Application Scenarios No Scenario Gain Value ...

Page 22: ...n the product determined by 2 EQ configuration input pins to dynamically change to different EQ modes The following shows the frequency response of each mode Mode GPIO8 GPIO7 Color Default 0 0 Gaming 0 1 Communication 1 0 Movie 1 1 Audio Precision 04 20 11 15 35 35 DA EQ SPDIF_In_DA_Out at27 Color Sweep Trace Line Style Thick Data Axis Comment 1 1 Red Solid 2 Anlr Ampl Left 00 2 1 Magenta Solid 2 ...

Page 23: ...ere be recording and producing and speaking sound or volume is being changed under little environment If the lasting low voice of volume AGC will enlarge volume then volume is sustained loudly while AGC will reduce volume Features Programmable AGC Parameters Selectable Gain from 12 dB to 45 dB in 1 dB Steps Selectable Attack Release and Hold Times AGC Enable Disable Function Limiter Enable Disable...

Page 24: ...1 CM6533DH USB Audio Chip Page 24 60 www cmedia com tw Rev 1 7 Copyright C Media Electronics Inc Input Signal Output Signal Max Threshold Max Threshold Attack time Hold time Release time Decrease Gain Hold Gain increase Gain ...

Page 25: ...4 start address of returned data L start_addr byte5 bit7 bit6 UART_INT bit5 GPI_INT bit4 SPIS_INT slave mode int bit3 SPIM_INT master mode int bit2 I2CS_INT slave mode int bit1 I2CM_INT master mode int bit0 IR_INT byte6 read data of start_addr byte7 read data of start_addr 1 byte8 read data of start_addr 2 byte9 read data of start_addr 3 byte10 read data of start_addr 4 byte11 read data of start_a...

Page 26: ...ed Input Data Format byte0 always 1 for org HID event report ID byte1 for defined HID event each event occupies one bit byte2 byte3 start address of returned data H start_addr byte4 start address of returned data L start_addr byte5 bit7 bit6 UART_INT bit5 GPI_INT bit4 SPIS_INT slave mode int bit3 SPIM_INT master mode int bit2 I2CS_INT slave mode int bit1 I2CM_INT master mode int bit0 IR_INT byte6 ...

Page 27: ...Format byte0 always 1 for org HID event report ID byte1 start address of write reg H start_addr byte2 start address of write reg L start_addr byte3 effective write read data length 12 byte4 write data to start_addr byte5 write data to start_addr 1 byte6 write data to start_addr 2 byte7 write data to start_addr 3 byte8 write data to start_addr 4 byte9 write data to start_addr 5 byte10 write data to...

Page 28: ...f Output Data 16 h 00 00 16 h 00 64 bytes Data Output Data Format Byte 0 Data of Reg wValue Byte 1 Data of Reg wValue 1 Byte 2 Data of Reg wValue 2 Byte 63 Data of Reg wValue 63 6 5 3 USB Vendor Requests bmRequestType bRequest wValue wIndex wLength Data 0x43 Vendor Other 0x01 Register Write Address 0x0000 Data Length 64 bytes Data 0xC3 Vendor Other 0x02 Register Read Address 0x0000 Data Length 64 ...

Page 29: ...hen write back to register 0x3E 3 When CS_SEL is changed to CS2 firmware will erase the whole flash automatically Repeat writing flash 6 6 SPDIF Control Description 6 6 1 SPDIF Frame Description Audio format linear 16 bit default Allowed sampling frequencies Fs of the audio 96KHz from DVD 88 2KHz from DVD 48 kHz from DAT 44 1kHz from CD One way communication from a transmitter to a receiver Contro...

Page 30: ...of SPDIF Preamble cell order cell order last cell 0 last cell 1 B 11101000 00010111 M 11100010 00011101 W 11100100 00011011 Preamble B Marks a word containing data for channel A left at the start of the data block Preamble M Marks a word with data for channel A that is not at the start of the data block Preamble W Marks a word containing data for channel B right for stereo When using more than 2 c...

Page 31: ...elA W ChannelA B ChannelA W ChannelA M ChannelA W Frame 191 Frame 0 Frame 1 SubFrame SubFrame Figure 2 Preamble Description of 192 SPDIF frame 6 6 2 SPDIF Out Channel Status bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 byte0 consumer professional audio non audio copyright pre emphasis mode default 0 P 0 P 1 P 0 P 0 fixed 0 fixed 0 fixed 0 fixed byte1 category code L default 0 P 0 P 0 P 0 P 0 P 0 P 0 P ...

Page 32: ...33X1 CM6533DH series IC provide digital microphone interface for recording There are two microphone signals transmitted on a single DATA line from DMIC module The oversampling bit stream output from DMIC module connects to internal decimation filter to generate PCM output CLOCK DATA1 DATA2 DAT A CLOCK L R GND IN VDD DAT A CLOCK DMIC Module MIC VDD CM6533 Series ...

Page 33: ...tion From Master to Slave From Slave to Master SCL 0 A A A A MAP Data 1 SDA 1 N Byte Write Transaction Slave Address 1 A Data 1 SDA 2 N Byte Read Transaction Slave Address A A from master to slave from slave to master High SDA e acknowledg not A Low SDA e acknowledg A Stop Stop MAP Memory Address Pointer the target register address in slave device SCL 1 A Data Slave Address Start Stop 0 A A MAP SD...

Page 34: ... The target slave device address 0xA8 POR 0 R W SA_reg 1 read 0 write 1 b0 POR 6 8 4 I2C Master Memory Address Pointer MAP Register Address 0x81 Bits R W Bit Mnemonic Description Default 7 0 R W MAP_reg The register low byte address of salve device to be read or written 8 b0 POR 6 8 5 I2C Master Memory Address Pointer MAP2 Register Address 0x82 Bits R W Bit Mnemonic Description Default 7 0 R W MAP...

Page 35: ...tatus Register 1 Address 0x94 Bits R W Bit Mnemonic Description Default 7 R W i2c_start Trigger I2C read write command 0 1 trigger I2C read write command 1 0 I2C interface had completed current task 0 I2C interface is idle and ready for work 1 I2C interface is running 1 b0 POR 6 R W i2c_reset Reset I2C interface 0 Not reset I2C interface 1 Reset I2C interface 1 b0 POR 5 R W map_len MAP length 0 8 ...

Page 36: ...ady WO Flag to index F W has prepared next data ready After prepare done F W need set this bit to index the data had been written If F W didn t catch on when all data has been transmitted the I2C clock would be keep low to till it ready 1 b0 POR 5 4 R W LD_BLOCK Download to which block of SRAM 00 Load to 1st 8KB block 01 Load to 2nd 8KB block 10 Load to 3rd 8KB block 11 Load to 4th 8KB block 2 b00...

Page 37: ...r Address 0x96 Bits R W Bit Mnemonic Description Default 7 W CHG_ENABLE MCU can program I2C clock 1 b1 enable 1 b0 POR 6 R W LD_SEL MCU download select 1 b0 SPI download 1 b1 I2C download 1 b0 POR 5 0 W CHG_FREQ Set I2C master clock period The clock period 83 3 5 CHG_FREQ 1 Ex CHG_FREQ 6 d48 I2C Clock Period 83 3 5 48 1 20408ns HW limitation CHG_FREQ 6 h3 6 h0 POR ...

Page 38: ...c Description Default 31 0 R W MCU_data0 F The data received from or transmitted to master device This register cannot be written when 2 wire slave serial bus status is busy 0000h POR 6 8 13 I2C Slave Status Register Address 34 35h Bits R W Bit Mnemonic Description Default 15 Reserved 1b 14 12 R Reserved 0h 11 R W Thld_int_mask Threshold interrupt mask 1 mask 0 non mask default 0 0b POR 10 R Write...

Page 39: ...0 14h as slave address 11 select 0001011 16h as slave address 01b POR 3 R W Sync_sel Synchronization Method Selection 1 Data synchronization When this bit is one if the current transaction has not been serviced by ARC the clock line of the 2 wire serial bus will be pulled low Under this situation the MCU cannot start a new transaction or continue the current read transaction until the clock line g...

Page 40: ...on status is used to signal a fail status to ARC In this case the driver should consider to repeat the failed Driver initiated transaction again 0 R W ack Driver Acknowledge means driver has processed the current transaction Write 1 to acknowledge This bit will be cleared automatically 0b POR I2C example for Master mode Write 2 bytes Slave address 92 MAP address 01 Data 55 AA Write 0x80 92 Slave a...

Page 41: ...be interpreted according to the individual codec The content of this register after a write operation completes has no meaning The content of this register after a read operation completes should reference the document of individual codec to see how many bits in this register is valid 0x0000 0000 POR 6 9 2 SPI Control Register 0 Address 3ch Bits R W Bit Mnemonic Description default 7 R W slv_mst S...

Page 42: ...ing mode 1 b0 POR 1 R W second_leading_bit Second data bit of 2 bit leading mode 1 b0 POR 0 R W leading_bit_mode RA8815 2 bit leading mode 0 No leading bits 1 2 bit leading for each transaction 1 b0 POR 6 9 4 SPI Interrupt Address 3eh Bits R W Bit Mnemonic Description default 7 R W CPOL Clock Polarity 1 b1 POR 6 R W CPHA Clock Phase 1 b1 POR 5 4 R W CS_SEL SPI CS Select 00 CS0 01 CS1 10 CS2 Defaul...

Page 43: ...Control Register 3 Address 3fh Bits R W Bit Mnemonic Description default 7 0 R W data_len The data length of read write 0000_0000 Reserved 0000_0001 1 bytes 0000_0010 2 bytes 0000_0011 3 bytes 1111_1111 255 bytes 8 d0 POR SPI example for master mode Write 3 bytes Address 92 DATA 55 AA Write 0x38 0x3A 92 55 AA Data register Write 0x3F 03 Write 3 bytes length Write 0x3D A0 SPI start Read 3 bytes Add...

Page 44: ...C5h Bits R W Bit Mnemonic Description Default 15 0 R W GPOE_0 GPOE_1 GPIO output enable register which represents for pin XGPIO 15 0 1 the corresponding pins are used as output 0 the corresponding pins are used as input 16 h0 POR 6 10 4 GPIO Interrupt Enable Mask Register Address Offset C6 C7h Bits R W Bit Mnemonic Description Default 15 0 R W GPI_EN GPIO_E GPIO interrupt enable mask which represe...

Page 45: ... enable D12 1 b1 GPI 12 remote wake up enable D13 1 b1 GPI 13 remote wake up enable D14 1 b1 GPI 14 remote wake up enable D15 1 b1 GPI 15 remote wake up enable 16 h0 POR 6 10 7 GPIO Pull up Down Address Offset 0xE4 Bits R W Bit Mnemonic Description default 7 R W GPIO_PD0 7 GPIO_7 pad control 1 b1 floating 1 b0 75k pull up 1 b1 POR 6 R W GPIO_PD0 6 GPIO_6 pad control 1 b1 floating 1 b0 75k pull up ...

Page 46: ... b1 POR 1 R W GPIO_PD1 1 GPIO_9 pad control 1 b1 floating 1 b0 75k pull up 1 b1 POR 0 R W GPIO_PD1 0 GPIO_8 pad control 1 b1 floating 1 b0 75k pull up 1 b1 POR Address Offset 0xE6 Bits R W Bit Mnemonic Description default 7 R W GPIO_PD2 7 GPIO23 pad control 1 b1 floating 1 b0 75k pull up 1 b1 POR 6 R W GPIO_PD2 6 GPIO_22 pad control 1 b1 floating 1 b0 75k pull up 1 b1 POR 5 R W GPIO_PD2 5 GPIO_21 ...

Page 47: ...tores it in corresponding memory banks The waveform data format must comply with the following specifications 1 16 bits PCM with 2 s complement 2 First word must define waveform length Length 9 0 byte1 2 0 byte0 7 0 3 Waveform length must less than 2046 4 Four memory banks Bank1 0x6000 0x67FF Length 0x6000 0x6001 Waveform data 0x6002 0x67FF Bank2 0x6800 0x6FFF Length 0x6800 0x6801 Waveform data 0x...

Page 48: ...he LED freq register value is equal to the LED duty register high the PWM output also goes high When the LED freq LED duty register reaches zero the PWM output is forced to go low The low to high ratio duty of the PWM output is LED duty LED freq LED duty LED freq LED unit 256 step PWM duty range 00H FFH 00 10 5ms 01 5 45ms 10 2 73ms 11 1 36ms 00H FFH FEH FFH 01H FFH 80H FFH FEH FFH The Output Duty...

Page 49: ...Flash Initial Time Read 32K Firmware from internal flash Reset Ready 55m sec 95m sec Default 1 sec 6 13 1 Watchdog Reset Timer The watchdog timer is a 15 bit counter that is incremented every 24 or 384 clock cycles It is used to provide the system supervision in case of software or hardware upset If the software was not able to refresh the Watchdog Timer after 786336 or 12581376 clock cycles 65ms ...

Page 50: ...ression algorithms will usually sacrifice some audio frequency signals It might result in flat thin and lifeless sounds Audio Brilliant recreates the subtleties of the original performance 7 4 Xear Dynamic Bass Xear Dynamic Bass reproduces the deep and vibrating bass in music games and movies and music even over small speaker headphone drivers and enclosures Applying psychoacoustic techniques to m...

Page 51: ...tion and audio encoding compression Dolby licenses its technologies to consumer electronics manufacturers 8 1 Dolby Headphone v2 Dolby Surround effect creates the sensation of multiple loudspeakers in a room and is closer to home theater sound than traditional headphone audio 8 2 Dolby Pro Logic IIx Dolby Pro Logic IIx expands stereo or 5 1 channel audio to 7 1 channel sound 8 3 Xear Environment E...

Page 52: ...ple Rate 48kHz 16Bits Operation HP Out Playback Mic In Recording EQ disable Spdif out disable No loading Parameter Min Typ Max Unit Total power consumption including Playback and Recording 65 9 Digital 27 9mA Analog 38mA mA Standby power consumption excluding Playback and Recording 64 mA Suspend mode power consumption 2 4 mA 9 4 DC Characteristics Test Conditions DV50 5V VDD 3 3V DGND 0V TA 25o C ...

Page 53: ...0 3 3 3 6 V CL 10uF Driver Output Impedance including the 22 External Serial Resistor RO D D 24 40 static LOW or HIGH Rise and Fall Times tr tf 3 10 19 ns CL 50 pF driver mode Rise Fall Time Matching MA_TRT F 90 110 CL 50 pF driver mode Crossover Voltage VXOVER 1 30 1 75 2 0 V CL 50 pF driver mode Differential Receiver Common Mode Range VCM_DR EC 0 8 2 5 V Single ended Receiver Threshold Voltage V...

Page 54: ...20KHz 87 dB 32Ω loading 20 20KHz 86 7 71 1KHZ dB Dynamic Range with 60dBFs Output Signal 10KΩ loading A Weighted 91 dB 32Ω loading A Weighted 92 dB Noise Level SNR with 96dBFs Output Signal 10KΩ loading A Weighted 93 dB 32Ω loading A Weighted 93 dB Inter Channel Phase Delay 100Hz 20kHz 0 01 1 01 Deg Sampling Frequency Accuracy 10KΩ loading 0 0046 0 0078 Channel Separation Crosstalk 10KΩ loading 20...

Page 55: ...itions Platform DELL Desktop 32BWS02 4G RAM Windows 8 1CHT Items Test Conditions Test Values Unit Min Typ Max Full Scale Input Voltage 0 74 Vrms THD N 3dB Full Scale Input 20 20KHz 85 83 1KHz dB Dynamic Range with 60dBFs Input Signal A Weighted 88 dB Sampling Frequency Accuracy Fs 48kHz 16bits 0 0032 0 0069 Fs 96kHz 24bits 0 0057 0 0078 Channel Separation Crosstalk 20 20KHz 80 dB Frequency Respons...

Page 56: ...ohms loading Master Volume 0dB Mic Gain 0dB Platform DELL Desktop 32BWS02 4G RAM Windows 8 1 CHT Items Test Conditions Test Values Unit Min Typ Max Full Scale Output Voltage 1 05 Vrms THD N 3dB Full Scale Input 20 20KHz 90 89 1KHz dB Dynamic Range with 60dBFs Input Signal A Weighted 92 dB Channel Separation Crosstalk 20 20KHz 90 dB Frequency Response 20 20KHz 0 036 20Hz 0 133 20KHz dB Passband Rip...

Page 57: ... Ambient Temperature Supply Range CM6533 48 Pin LQFP 7mm 7mm 1 4mm Plastic 15 C to 70 C DVdd 5V AVdd 5V CM6533N 48 Pin QFN 7mm 7mm 0 85mm Plastic 15 C to 70 C DVdd 5V AVdd 5V CM6533X1 48 Pin LQFP 7mm 7mm 1 4mm Plastic 15 C to 70 C DVdd 5V AVdd 5V CM6533DH 48 Pin LQFP 7mm 7mm 1 4mm Plastic 15 C to 70 C DVdd 5V AVdd 5V Outline Dimensions Dimensions shown in inches and mm ...

Page 58: ...6533 CM6533N CM6533X1 CM6533DH USB Audio Chip Page 58 60 www cmedia com tw Rev 1 7 Copyright C Media Electronics Inc 11 1 Package Dimension of CM6533 6533X1 6533DH 48 Lead Thin Plastic Quad Flatpack LQFP ...

Page 59: ...CM6533 CM6533N CM6533X1 CM6533DH USB Audio Chip Page 59 60 www cmedia com tw Rev 1 7 Copyright C Media Electronics Inc 11 2 Package Dimension of CM6533N 48 Lead Thin Plastic Quad Flatpack QFN ...

Page 60: ...r Information furnished by C Media Electronics Inc is believed to be accurate and reliable However no responsibility is assumed by C Media Electronics Inc for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications are subject to change without notice No license is granted by implication or otherwise under any patent or patent right...

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