ProDAQ 3411 24-Ch. ADC Function Card User Manual
3411-XX-UM
Copyright,
1998-2009 Bustec Production Ltd.
Page 35 of 40
A.1.7 MODE Register
The function card ID register contains a unique number used to identify the card.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Operation RW RW RW
--
RW
--
RW RW RW RW RW RW
--
--
--
--
Initial
0
0
0
X
0
X
0
0
0
0
0
0
0
0
0
0
Content FIDC FIDD ADAI n/u ATC n/u
DSC
CSC n/u FIRS FIEN
not used
FIEN
Enables the FIFO for pattern capture/generation.
FIRS
Resets the FIFO.
CSC
Selects the base unit for the data acquisition clock (DIVCLK). A zero (“0”) selects a base
clock of 3.2 µs, a one (“1”) a base clock of 102.4 µs.
DSC
Selects the base unit for the delay timer (DELAY). A zero (“00”) selects a base unit of 1.6 µs,
a one (“01”) a base unit of 25.6 µs, a two (“10”) a base unit of 409.6 µs and a three (“11”) a
base unit of 6553.6 µs.
ATC
Enables the data acquisition in continuous mode.
ADAI
Enables the data acquisition to run infinitive. Otherwise it will stop after the number of scans
programmed in the REPCOUNT register.
FIDD
Disable the FIFO drop mode (enabled by default).
FIDC
enable FIFO clock.
A.1.8 REPCOUNT Register
This register holds the repetition counter for the data acquisition.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Operation RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Initial
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Content
Repetition Counter
The repetition counter is a 16-bit down counter used to specify how many scans shall be
performed. The number of scans performed is the register value plus one.
A.1.9 PATA Register
Defines which channel takes part in the data acquisition. The PATA register helds the mask for
channels 1 ...16.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Operation RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Initial
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Content CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
