3411-XX-UM
ProDAQ 3411 24-Ch. ADC Function Card User Manual
Page 16 of 40
Copyright,
1998-2009 Bustec Production Ltd.
3.3. Multiplexed Conversion
To acquire consecutive samples from multiple input channels, the ProDAQ 3411 features a data
acquisition mode where the control logic automatically switches the input multiplexer between the
enabled channels and moves the converted values of such a scan into the on-board FIFO. The
FIFO logic allows generating asynchronous signals to the application when data is available.
3.3.1. Channel Mask
To specify which channels should take part in a scan a channel mask is used. The channel mask
consists of two 16-bit registers (PATA and PATB), where the single bits represent the 24 input
channels and the two internal channels. The two internal channels are channel 25, which is
internally connected to analog ground and channel 26, which is connected to the voltage reference
bus from the motherboard. Bits 0 to 15 in the PATA register represent channel 1 to 16, while the
lower 10 bits of the PATB register represent channels 17 to 26. Setting a bit to one (“1”) in the
channel mask enables the respective channel; setting a bit to zero (“0”) disables the channel.
3.3.2. Scanning
When the data acquisition is started, the control logic switches the input multiplexer to the first
channel enabled in the channel mask, waits for a specified time to allow the gain and filter stage to
settle to this new signal level and starts the ADC to convert the signal. The resulting data word is
moved into the on-board FIFO. Then the multiplexer is switched to the next enabled channel, the
data is converted and so on (see Figure 4 - Scan Timing).
Figure 4 - Scan Timing
The timing between these scans, the scan rate, can be generated by using the on-board clock, a
trigger signal from the motherboard or the front-panel input or can be generated by a software
command. Each pulse of either one of these sources will start a scan over the enabled channels.
3.3.3. Data Conversion
After the input multiplexer is switched to a channel, the gain and filter stages need enough time to
settle to this new analog voltage level. This time is in minimum 51 µs (filter bypass mode) and
needs to be taken in consideration when setting up the card for data acquisition (see Figure 5 -
Conversion Timing).
Ch. 1
Ch. 2
Ch. 3
Ch. 4
Ch. 5
Ch. n
Time
Scan Rate
(or per-channel sample rate)
Remark: A above denotes that the input multiplexer is
switched to the respective channel in that time.
