Bruker DAEDALUS, Service Manual

Page: 21 / 145

Design
Daedalus Lock Manual Spectrospin AG 15
Design 2.4
The Digital Lock is located on three boards. The Receiver and Transmitter are both
contained in a moulded 19 inch high frequency housing. The Digital Synthesizer
and the Pulse Section (old PFP) are located on the Transmitter. The entire frequency
generation is based on a 10 MHz reference. The Power, Gain, Phase, Mode and Shift
settings are conducted through a serial Bus from the Controller Board. The settings
are reclocked to the Controller and checked with the originals as verification. The
galvanic isolation of the Bus is located on the Transmitter.
The Bus is looped from the Transmitter to the Receiver for the Lock Gain setting.
The IF-Signals (Dispersion, Absorption) are digitized in the Receiver and are serial-
ly forwarded to the Controller Board via optocouplers. The sampling rate proceeds
at 13.3 kHz per channel. There are some other diagnostic signals which are digitized
with the same A/D-Converter for diagnostic purposes.
The Controller Board receives all User or X32 commands via the VME Interface.
The 80535 microprocessor is the central element of the lock system; it receives,
processes and sends the commands to the various boards. All digital signal process-
ing, including mixing, regulating and filtering, takes place in the Signal Processor.
Display data for the X32 (lock line) is produced in the DSP and sent in serial form
via optocouplers to the GT01 board. The H0 power source is the only analog part lo-
cated on the Cotroller Board. It is also managed by the DSP.