CHAPTER II -4
1.3.2
ASIC
The ASIC is composed of a Cell Based IC that contains the following functional blocks.
(1)
Oscillator circuit
Generates the main clock for the CPU by dividing the source clock frequency by two.
(2)
Address Generator
Generates the address bus by latching the AD bus with the ALE signal.
(3)
Address decoder
Generates the CS signal for each device.
(4)
DRAM control
Generates the RAS, CAS, WE, OE and MA signals for the DRAM and controls the
refresh processing (CAS before RAS self-refreshing method).
(5)
Interrupt control
Interrupt levels:
Priority
High
9
TIMER 3 (Watch Dog)
8
MONITOR
7
FIFO
6
EXINT
5
TIMER 1
4
BD
3
SPARE
2
CDCC / BOISE / DATA EXTENTION
Low
1
TIMER 2
Note: All the interrupts can be masked.
(6)
Timers
The following timers are included:
Timer 1
16-bit timer
Timer 2
10-bit timer
Timer 3
Watch-dog timer
(7)
FIFO
A 10Kbit FIFO is included. Data for one raster is transferred from the RAM to the
FIFO by DMA transmission and is output as serial video data. The data cycle is
6.13mhz.
Summary of Contents for HL HL-1060
Page 1: ...SERVICE MANUAL MODEL HL 1060 R LASER PRINTER ...
Page 24: ...CHAPTER II 8 1 3 5 DRAM Four 4Mbit DRAM x 8bit are used as the printer memory Fig 2 7 ...
Page 28: ...CHAPTER II 12 1 3 11 Engine I O Fig 2 13 shows the engine interface circuit Fig 2 13 ...
Page 96: ...Appendix 3 Main PCB Circuit Diagram 1 4 CODE UK3400000 B48K246CIR NAME V 3 ...
Page 97: ...Appendix 4 Main PCB Circuit Diagram 2 4 CODE UK3400000 B48K246CIR NAME V 4 ...
Page 98: ...Appendix 5 Main PCB Circuit Diagram 3 4 CODE UK3400000 B48K246CIR NAME V 5 ...
Page 99: ...Appendix 6 Main PCB Circuit Diagram 4 4 CODE UK3400000 B48K246CIR NAME V 6 ...
Page 100: ...Appendix 7 Driver PCB Circuit Diagram CODE UK3634000 B48K280CIR NAME V 7 ...
Page 105: ...Appendix 12 SR PCB Circuit Diagram CODE UK3653000 B48K284CIR NAME V 12 ...
