Broadcast Electronics AM-2.5E, User Manual

Page: 234 / 320

1-23
1-104.
MONO MODE SWITCHING.
Left and right channel audio from the input circuit is
applied to monophonic mode selection integrated circuit U39. U39 is controlled by:
1) mono L, mono R, and mono SC signals from the stereo circuit board and 2) mono left or
mono right channel select jumper P4. If the transmitter is equipped with the stereo
circuit board and monophonic operation is required, LOW control signals from the
following control lines are applied to configure U39 to select the desired monophonic
audio: 1) mono SC control line and 2) mono L or mono R control lines. If the transmitter
is not equipped with the stereo circuit board, jumper P4 is installed in the left or right
channel position to configure U39 to select left or right channel audio for monophonic
operation. The output of U39 is applied to single channel monophonic boost amplifier
U8A. The monophonic boost circuit is designed to provide up to 6 dB of additional gain
for monophonic operations. This level allows the transmitter to operate at 100%
modulation. Potentiometer R41 allows the adjustment of the monophonic boost level. A
monophonic boost control in most audio processing equipment also provides additional
gain for monophonic conditions. If the transmitter is configured for stereo operation, U39
sums the left and right channels to produce the stereo L+R information. The L+R
information is applied through monophonic boost circuit U8A to the 24 uS delay circuit.
1-105.
24 uS DELAY CIRCUIT.
Integrated circuits U8B, U9A, and U9B are configured as a 24
uS delay circuit. The delay circuit is incorporated into the L+R audio path to ensure all
required stereo equalization will be performed in the L-R audio path. This eliminates the
requirement for complex adjustable delay circuitry in the L+R path.
1-106.
NEGATIVE LIMITER.
The output from the delay circuit is applied to a negative limiter
circuit. The circuit consists of integrated circuit U14A, diodes D1 and D2, and negative
limit control R76. The circuit is designed to prevent the loss of carrier during negative
modulation. Potentiometer R76 allows the circuit to be adjusted from 90% to 100%. The
output of the limiter is applied a incidental-phase-modulation (IPM) correction circuit
and a PWM circuit. A sample from the negative limiter circuit is applied to comparator
U43. When the negative limiter circuit is enabled, the output of U43 will go high to
illuminate negative limiter indicator DS5.
1-107.
IPM CORRECTION CIRCUIT.
L+R audio from negative limiter U14A is applied through
buffer U15A to a low-pass filter. The filter is a fifth order low-pass filter consisting of
integrated circuits U15B and U16A. The filter is designed to provide: 1) the correct time
delay for IPM correction and 2) the correct frequency response for L+R metering. The
output from the filter: 1) is applied to inverting buffer U16B and 2) provides an IPM
adjust signal to the IPM corrector circuit. Buffer U16B inverts the L+R signal and
removes a dc sample introduced by the negative limiter. The output of U16B is applied to
the L+R metering circuitry.
1-108. A power control PWM signal from the controller circuit board is applied to low-pass filter
U17B. U17B is designed to convert the power control PWM signal to a dc control voltage.
The output of U17B is applied to inverting amplifier U17A. The output of U17A provides
an IPM power reference signal to the IPM wave shape circuit.
1-109.
PWM CIRCUIT.
L+R audio from the negative limiter circuit is applied to amplifier U14B.
U14B amplifies the L+R signal to a 4 volt peak-to-peak level with a -0.5 volt dc potential.
This provides a 40% nominal duty cycle at the output of a PWM comparator to allow the
circuitry to modulate the transmitter from -100% to +150%. The output of U14B is
applied to high-speed PWM comparator U22A. U22A compares the L+R signal with a
reference signal from integrator U12 to generate a square-wave PWM control signal. The
square wave duty cycle varies in response to the L+R audio level. The output of U22A is
applied to the PWM driver circuit and an exciter failure detector circuit.