36
4.4 Chipset Features Setup
This section allows you to configure the system based on the
specific features of the installed chipset. This chipset manages bus
speeds and the access to the system memory resources, such as
DRAM and the external cache. It also coordinates the
communications between the conventional ISA and PCI buses. It
must be stated that these items should never be altered. The default
settings have been chosen because they provide the best operating
conditions for your system. You might consider and make any
changes only if you discover that the data has been lost while using
your system.
CMOS Setup Utility
-
Copyright ©1984-2001 Award Software
Advanced Chipset Features
Item Help
SDRAM RAS-to CAS Delay
[3]
Menu Level
X
SDRAM RAS Precharge Time
[3]
SDRAM CAS latency Time
[3]
SDRAM Precharge Control
[Enabled]
DRAM Data Integrity Mode
[Non-ECC]
System BIOS Cacheable
[Enabled]
Video BIOS Cacheable
[Enabled]
Video RAM Cacheable
[Enabled]
8 Bit I/O Recovery Time
[3]
16 Bit I/O Recovery Time
[2]
Memory Hole At 15M-16M
[Disabled]
AGP Aperture Size (MB)
[64]
Power-Supply Type
[Auto]
:
Move Enter
:
Select + / - /PU/PD
:
Value F10
:
Save ESC
:
Quit F1
:
General Help
F5
:
Previous Values F6
:
Fail-Safe Defaults F7
:
Optimized Defaults
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