16
must constantly proceed a Refresh cycle to Watchdog Timer before its
period setting comes ending of every 1, 2, 10, 20, 110 or 220 seconds
which pre-setting by JP8(5-10). If the Refresh cycle does not active
before Watchdog Timer period cycle, the on board Watchdog Timer
architecture will issue a Reset or NMI cycle to the system.
JP8 (5-10) : Watchdog Timer - Out Period
PERIOD
JP8(5-6)
JP8(7-8)
JP8(9-10)
*1 sec
ON
ON
ON
2 sec
OFF
ON
ON
10 sec
ON
OFF
ON
20 sec
OFF
OFF
ON
110 sec
ON
ON
OFF
220 sec
OFF
ON
OFF
The Watchdog Timer is control by two I/O ports.
443H
I/O Read The Enable cycle.
443H
I/O Read The Refresh cycle.
045H
I/O Read
The Disable cycle.
The following sample programs showing how to Enable, Disable
and Refresh the Watchdog Timer:
WDT_EN_RF
EQU 0443H
WDT_DIS
EQU
0045H
WT_Enable
PUSH
AX
; keep AX DX
PUSH
DX
MOV
DX,WDT_EN_RF
; enable the watch-dog timer
IN
AL,DX
POP
DX
; get back AX, DX
POP
AX
RET
WT_Rresh
PUSH
AX
; keep AX, DX
PUSH
DX
MOV
DX,WDT_ET_RF
; refresh the watch-dog timer
IN
AL,DX
POP
DX
; get back AX, DX
POP
AX
RET
WT_DISABLE
PUSH AX
PUSH
DX
MOV
DX,WDT_DIS
; disable the watch-dog timer
IN AL,DX
POP
DX
; get back AX, DX
POP
AX
RET
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