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38

APPENDIX

208-LEAD MQFP PIN

208

207

206

205

204

203

202

201

200

199

198

197

196

195

194

193

192

191

189

188

187

186

185

184

183

182

181

180

190

179

178

177

175

174

173

172

171

170

176

169

168

167

165

164

163

162

161

160

159

158

157

166

71

72

73

74

75

76

77

78

79

80

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

81

82

83

84

86

87

88

89

90

85

91

92

93

94

96

97

98

99

95

10

0

10

1

102

103

104

5

4

3

2

7

6

9

8

1

14

13

12

11

16

15

17

10

19

18

23

22

21

20

25

24

27

26

29

28

32

31

30

34

33

36

35

40

39

38

37

41

43

42

45

44

50

49

48

47

46

52

51

152

153

154

155

150

151

156

148

149

143

144

145

146

141

142

140

147

138

139

134

135

136

137

132

133

130

131

128

129

125

126

127

123

124

121

122

120

117

118

119

116

114

115

112

113

107

108

109

110

111

105

106

OO

BMSTR

PIN 1
IDENTIFIER

VDD

CS

SBTS

GND

WR

RD

GND

VDD

GND

REDY

SW

CPA

VDD

VDD

GND

ACK

MS0

MS1

GND

GND

MS2

MS3

FLAG11

VDD

FLAG10

FLAG9

FLAG8

GND

DATA0

DATA1

DATA2

VDD

DATA3

DATA4

DATA5

GND

DATA6

DATA7

DATA8

VDD

GND

VDD

DATA9

DATA10

DATA11

GND

DATA12

DATA13

NC

NC

DATA14

NC

IRQ2

IRQ1

IRQ0

GND

NC

NC

FLAG3

VDD

VDD

RSF0

GND

RCLK0

DR0A
DR0B

TFS0

TCLK0

VDD

GND

DT0A
DT0B
RFS1

GND

RCLK1

DR1A
DR1B

TFS1

TCLK1

VDD
VDD

DT1A
DT1B

PWM EVENT1

GND

PWM EVENT0

BR1
BR2

VDD

CLKIN

XTAL

VDD

GND

SDCLK1

GND

VDD

SDCLK0

DMAR1
DMAR2

HBR
GND

RAS

SDWE

VDD

DQM

SDCKE

SDA10

GND

DMAG1
DMAG2

HBG

GND
GND
BMS
BSEL
TCK
GND
TMS

TDI
TRST
TDO
EMU
ID0
ID1
NC
VDD
VDD

GND

GND

VDD

VDD

GND

GND
VDD

VDD
GND

GND

VDD

DATA15
GND
VDD

VDD

FLAG2

FLAG1

FLAG0

GND

ADDR0

ADDR1

ADDR2

VDD

VDD

ADDR3

ADDR4

ADDR5

GND

GND

ADDR6

ADDR7

ADDR8

VDD

GND

ADDR9

ADDR10

ADDR11

GND

VDD

ADDR12

ADDR13

ADDR14

VDD

ADDR15

ADDR16

ADDR17

GND

GND

ADDR18

ADDR19

ADDR20

VDD

ADDR21

ADDR22

ADDR23

GND

VDD

RESET

CAS

DATA16

DATA17

DATA18

DATA19

DATA20

DATA22
DATA21
NC

DATA23

DATA24

DATA25

DATA26

DATA27

DATA28

DATA29

DATA30

DATA31

FLAG7

FLAG6

FLAG5

FLAG4

NC = NO CONNECT

TOP VIEW

(Not to Scale)

ADSP-21065L

SPORT 1

4

IOP

REGISTERS

(MEMORY MAPPED)

CONTROL,

STATUS, TIMER

&

DATA BUFFERS

I/O PROCESSOR

INSTRUCTION

CACHE

32  

 48 BI

T

DATA

ADDR

TWO  INDEPENDENT

DUAL-PORTED BLOCKS

PROCESSOR PORT

I/O PORT

BLOCK 0

BLOCK 1

JTAG

TEST &

EMULATION

7

HOST PORT

ADDR BUS

MUX

IOA

17

IOD

48

MULTIPROCESSOR

INTERFACE

DUAL-PORTED SRAM

EXTERNAL

PORT

DATA BUS

MUX

32

24

24

PM ADDRESS BUS

DM ADDRESS BUS

PM DATA BUS

DM DATA BUS

BUS

CONNECT

(PX)

DATA

REGISTER

FILE

1

6

  
 40 

BIT

BARREL

SHIFTER

ALU

MULTIPLIER

32

48

40

CORE PROCESSOR

DMA

CONTROLLER

PROGRAM

SEQUENCER

DAG2

8  

 4  

 24

SDRAM

INTERFACE

(I

2

S)

(2 Rx, 2Tx)

(2 Rx, 2Tx)

(I

2

S)

SPORT 0

DAG1

8  

 4  

 32

DATA

DATA

DATA

ADDR

ADDR

ADDR

Functional Block Diagram

ADSP-21065 Digital Signal Processor (DSP)

Pin

Pin

Pin

Pin

Pin

Pin

Pin

Pin

Pin

Pin

No.

Name

No.

Name

No.

Name

No.

Name

No.

Name

1

VDD

43

CAS

85

VDD

127

DATA28

169

ADDR17

2

RFS0

44

SDWE

86

DATA3

128

DATA29

170

ADDR16

3

GND

45

VDD

87

DATA4

129

GND

171

ADDR15

4

RCLK0

46

DQM

88

DATA5

130

VDD

172

VDD

5

DR0A

47

SDCKE

89

GND

131

VDD

173

ADDR14

6

DR0B

48

SDA10

90

DATA6

132

DATA30

174

ADDR13

7

TFS0

49

GND

91

DATA7

133

DATA31

175

ADDR12

8

TCLK0

50

DMAG 1

92

DATA8

134

FLAG7

176

VDD

9

VDD

51

DMAG 2

93

VDD

135

GND

177

GND

10

GND

52

HBG

94

GND

136

FLAG6

178

ADDR11

11

DT0A

53

BMSTR

95

VDD

137

FLAG5

179

ADDR10

12

DT0B

54

VDD

96

DATA9

138

FLAG4

180

ADDR9

13

RFS1

55

CS

97

DATA10

139

GND

181

GND

14

GND

56

SBTS

98

DATA11

140

VDD

182

VDD

15

RCLK1

57

GND

99

GND

141

VDD

183

ADDR8

16

DR1A

58

WR

100

DATA12

142

NC

184

ADDR7

17

DR1B

59

RD

101

DATA13

143

ID1

185

ADDR6

18

TFS1

60

GND

102

NC

144

ID0

186

GND

19

TCLK1

61

VDD

103

NC

145

EMU

187

GND

20

VDD

62

GND

104

DATA14

146

TDO

188

ADDR5

21

VDD

63

REDY

105

VDD

147

TRST

189

ADDR4

22

DT1A

64

SW

106

GND

148

TDI

190

ADDR3

23

DT1B

65

CPA

107

DATA15

149

TMS

191

VDD

24

PWM_EVENT1

66

VDD

108

DATA16

150

GND

192

VDD

25

GND

67

VDD

109

DATA17

151

TCK

193

ADDR2

26

PWM_EVENT0

68

GND

110

VDD

152

BSEL

194

ADDR1

27

BR1

69

ACK

111

DATA18

153

BMS

195

ADDR0

28

BR2

70

MS 0

112

DATA19

154

GND

196

GND

29

VDD

71

MS 1

113

DATA20

155

GND

197

FLAG0

30

CLKIN

72

GND

114

GND

156

VDD

198

FLAG1

31

XTAL

73

GND

115

NC

157

RESET

199

FLAG2

32

VDD

74

MS 2

116

DATA21

158

VDD

200

VDD

33

GND

75

MS 3

117

DATA22

159

GND

201

FLAG3

34

SDCLK1

76

FLAG11

118

DATA23

160

ADDR23

202

NC

35

GND

77

VDD

119

GND

161

ADDR22

203

NC

36

VDD

78

FLAG10

120

VDD

162

ADDR21

204

GND

37

SDCLK0

79

FLAG9

121

DATA24

163

VDD

205

IRQ 0

38

DMAR 1

80

FLAG8

122

DATA25

164

ADDR20

206

IRQ 1

39

DMAR 2

81

GND

123

DATA26

165

ADDR19

207

IRQ 2

40

HBR

82

DATA0

124

VDD

166

ADDR18

208

NC

41

GND

83

DATA1

125

GND

167

GND

42

RAS

84

DATA2

126

DATA27

168

GND

208-LEAD MQFP PIN CONFIGURATION

Summary of Contents for Personalized Amplification System

Page 1: ...ntrol 5 Figure 5 DSP Functional Block Diagram 7 Figure 6 DC Power Supply Block Diagram 7 Table 1 Adjustable Controls Gain range and nominal settings 12 Table 2 Nominal and Peak Signal Levels 13 Table 3 LED Trigger Levels 14 Figure 7 Nominal Bass Configuration 2 Bass Modules 14 Figure 8 Light Bass configuration 15 Figure 9 External power stand total of 4 bass modules 15 Figure 10 Heavy Bass total o...

Page 2: ...IED HEREIN INDICATE A POTENTIAL SHOCK HAZARD THAT MUST BE ELIMI NATED BEFORE RETURNING THE UNIT TO THE CUSTOMER B Insulation Resistance Test Cold Check 1 Unplug the power supply and connect a jumper wire between the two prongs of the plug 2 Turn on the power switch of the unit 3 Measure the resistance with an ohmmeter between the jumpered AC plug and each exposed metallic cabinet part on the unit ...

Page 3: ...3 THEORY OF OPERATION Figure 1 PS1 signal flow Diagram ...

Page 4: ...Remote control The ability to receive analog signal input and SPDIF digital signal input The ability to output analog signal and SPDIF digital signal Channel volume control Master volume control Mixer Tone control 100 sets of parameter equalizer System equalizer for compensating speaker characteristic Noisegate Limiter Clip indicator DSP software update and 100 sets of preset coefficients update P...

Page 5: ...nput signal headroom is 2 1Vrms max A user could operate the system from the input panel and the remote refer to figures 3 and 4 Figure 3 Powerstand Input and Output Connections Figure 4 R1 Remote Control THEORY OF OPERATION Channel 1 2 Unbal Unbal Channel 3 4 Power amp patch bass remote and AC power connections TRS Bal Unbal Commercial Audio P r oduct 917D R1 remote control 0 0 12 12 CH2 HIGH MID...

Page 6: ... 2 C8 For Channel 1 or 2 the signal is input either through the balanced XLR connector or through the unbalanced connector The connector has a very high impedance 900k ohms to allow direct connection of passive guitars or bass guitars The signal is then amplified by the adjust able pre amplifier After the pre amplifier the signal can be accessed at the balanced XLR line level output Next the signa...

Page 7: ... 24V 27V and 27V Refer to the block diagram below Figure 6 DC Power Supply Block Diagram THEORY OF OPERATION DSP Processing Block Diag Ch1 2 Preset Remote Ch1 In Ch2 In Ch 3 In Ch 4 In Hi Out Bass Out Sys EQ X Over Hi L R S DATA Out Limiter User EQ Preset EQ NoiseGate User EQ Preset EQ NoiseGate to SPDIF Master Vol Range 80 to 22dB 10 12 00 Sys EQ X Over Lo Limiter Knee 1 5dBV ...

Page 8: ...lose time of switch circuit to regulate the transformer primary1 accord ingly the voltage of transformer1 secondary will keep stable Of course in this way the effect of stabilization for 3 3V is best and that for other voltage is worse The regulation of the power supply for AMP is like this we get the 27V as feedback signal and send it to switch control auxiliary circuit2 When system works if 27V ...

Page 9: ... CheckSum to the DSP The communication adopts software simulation UART with two I O pin as RX and TX Communication rate is 4800bps add start bit and stop so every sending byte has 10 bits Data is send according to frame format every data check sum DSP will transfer a frame every 100ms and every sending will take about 30ms Control channel volume IC Because the design requires that the channel sign...

Page 10: ... U386 U385 U387 U431 and U435 include the following functions U386 Two channels of 24 bit ADC one for Ch1 analog input and one for Ch2 analog input The ADC will input signal levels in levels in excess of 2Vrms Master mode U385 Two channels of 24 bit ADC one for Ch1 analog input and one for Ch2 analog input The ADC will input signal levels in levels in excess of 2Vrms Slave mode U387 Two channels o...

Page 11: ...h 18 are used An external data bus 32 bits of which 8 are used Bus control signals Finally the signals are brought out through a D A stereo converter The left channel contains the signal for the L1 the right channel the signal for the bass module The L1 signal is routed to power amps 1 and 2 the B1 signal to power amp 3 The B1 signal is also available as a balanced signal at the Bass Line Out TRS ...

Page 12: ...y in software through the digital limiter and still offers good signal to noise properties 1 2 2 Gains and Signal Levels First we need to define some reference levels for all the adjustable controls in the system For the nominal signal levels we assume certain settings in those controls and define the gain of each adjustable section Table 1 Adjustable Controls Gain range and nominal settings Next ...

Page 13: ...ed This nominal the output level of a Shure SM58 microphone that is exposed to 104 dBSPL Mic Trim 12 00 21 dBV balanced 3 dBV Balanced Mic Trim min 8 dBV balanced 10dBV balanced This nominal the output level of an AKG C4000 microphone that is exposed to 120 dBSPL Ch1 Ch2 Line out XLR 6 dBV balanced 24 dBV balanced Dig Vol Control input 0 dBV 18dBV Dig Vol Control output 10 dBV 18dBV The nominal ga...

Page 14: ...utput for e g bass players or a kick drum To this end we have provided the Bass Send output on the power stand that can be connected to the All Amps In input of a second power stand That second power stand does NOT have any line arrays con nected but can drive between 1 and 6 additional bass modules Figures 7 10 show typical configurations Figure 7 Nominal Bass Configuration 2 Bass Modules THEORY ...

Page 15: ...configuration Figure 9 External power stand total of 4 bass modules THEORY OF OPERATION Light Bass Bass Send All Amps In External Power Stand With 2 Bass Modules Bass Send All Amps In External Power Stand With 2 Bass Modules ...

Page 16: ...ing how many bass modules are connected to the second external power stand and currently there is no user interface that would allow the user to specify that in any way There fore we have chosen to implement a constant drop of 6 dB whenever something is connected to the bass send output This will work perfectly for the first 3 cases in Table 5 but lead to exces sive bass in the last 2 cases The am...

Page 17: ...e A simple way to switch between the different modes is to create a dummy cable that brings out pins 2 and 2 to a banana plug The modes can be switched by applying different numbers of 10k ohm resistors or a short between the leads of the banana plug Pins 1 and 1 of the dummy cable can still be routed to a Speakon connector to attach B1 bass modules THEORY OF OPERATION Number of Bass Modules Imped...

Page 18: ...d to power the cooling fans sheet 2 D3 which are in turn driven in proportion to the output signal level 24V is also used to provide phantom power for the micro phone inputs 5 and 3 3V outputs are used primarily to power the DSP A D D A converters microcontrollers remote control communications etc The 15V outputs power the numerous OpAmps and other analog circuitry 1 5 Audio Signal Path 1 5 1 Gene...

Page 19: ...look up table to access a subset of these steps This optimizes the feel of the control over the range of 0 to 40dB The range is restricted to prevent the user from inadvertently turning the signal path completely off 1 5 5 Channel Insert J105 and J106 input panel PCB sheet 1 B5 are stereo jacks configured with the output Send connected to the Ring terminal and the input Return connected to the tip...

Page 20: ...er to be driven separately this would gener ally only be used in special applications where a single slave PS1 is used to add bass from two different master PS1 s 1 5 10 Power Amplifiers Note Refer to the Digital Amplifier PCB schematic sheets for the following information Each of the PS1 s 3 amplifier channels is implemented with a 2 chip Class D solution from Philips The three identical channels...

Page 21: ...ital Converters Digital Both A D converters U385 U386 and the D A U387 are hardware configured U386 is config ured as a master and U385 as a slave The DSP can reset the A D through FLAG3 and the D A through FLAG2 The data is received by the DSP on SPORT1 serial port 1 channel A U385 and channel B U386 The DSP transmits the audio data again on SPORT1 serial port 1 channel A to the D A U387 and chan...

Page 22: ...d though FLAG10 1 8 Microcontroller 1 8 1 Overview The microcontroller is clocked by X341 D3 12 MHz and provides interfaces between nearly all peripherals Table 6 Peripheral pins on the microcontroller 1 8 2 Interface to Remote Relay of DSP information to the Remote The DSP in the power stand needs to transfer the clip state channel volume data cause the table for channel volume in the DSP system ...

Page 23: ... In this chapter we describe how most of the functions are implemented 1 9 1 Gain Staging Gain staging is the process of properly adjusting the gain of the system The goal is to set the gains as high as possible to optimized signal noise without overdriving or clipping any elec tronic components In contrast to home audio products musical instrument and microphones have a large variation of output ...

Page 24: ...h is a 1 kHz band pass filter telephone sound In addition to the spectral EQ there is also a noise gate available 1 9 6 Bass Line Out Detection The microcontroller polls the normalling switch on the Bass Line Out connector in regular inter vals and transfers its state to the DSP If the DSP detects a change in the state it will mute the entire power stand latch in new system EQ coefficients through...

Page 25: ... muting circuitry comprised of Q810 Q811 DZ805 R895 and C959 digital amplifier PCB sheet 3 D2 is responsible to mute any noise coming out from the output of U387 CS4392 Digital to Analog converter The principle is to detect the voltage VDDA falling below 22 volts This will cut off the DZ805 Zener diode and Q810 NPN transistor This in turn will turn on Q811 NPN transistor and pull the voltage of U8...

Page 26: ...dedicated passive unit that houses two 5 1 4 drivers The input is via two 4 pole Neutrik Speakon connectors on the rear panel Both of these inputs are paralleled allowing you to jumper multiple bass modules together There are no crossover or protection ciricuit components located on the input panel All EQ and protection is performed in the PS1 power stand Pins 1 and 1 of the input connector are us...

Page 27: ...hat the Line In 20dB gain and the Phantom Power push buttons are not pushed in 1 3 Using a balanced XLR male input cable apply a 1 kHz 30dBV signal to the channel 1 input 1 4 Reference a dB meter to the input level Measure the gain output at the Amp 1 OUT jack It should be 48 5 dB 3dB 1 5 Move the shorting plug from the Amp 2 IN jack to the Amp 1 IN jack and repeat steps 1 1 to 1 4 for the channel...

Page 28: ...e Line In 20dB gain and the Phantom Power push buttons are not pushed in 4 3 Using an unbalanced 1 4 phono jack input cable apply a 1 kHz 10dBV signal to the channel 1 input 4 4 Reference a dB meter to the input level Measure the gain output at the Amp 1 OUT jack It should be 28 5 dB 4dB 4 5 Move the shorting plug from the Amp 2 IN jack to the Amp 1 IN jack and repeat steps 4 1 to 4 4 for the chan...

Page 29: ...nce a dB meter to the input level Measure the gain output at the Bass Amp 3 OUT jack It should be 40 1dB 3dB 7 5 Repeat steps 7 1 to 7 4 for the channel 4 Line input TEST PROCEDURES 8 Channel 3 and 4 Line Input Frequency Reponse and Distortion Tests 8 1 Place a 1 4 mono shorting plug into the Amp 1 IN and Amp 2 IN jacks on the right hand side of the input output panel This will disable the channel...

Page 30: ...nal to the transducer assembly 2 4 Listen carefully for any extraneous noises such as rubbing scraping or ticking TEST PROCEDURES Note To distinguish between normal sus pension noise and rubs or ticks displace the cone slightly with your fingers If the noise stays the same it is normal suspension noise and the driver is good Suspension noise will not be heard with program mate rial 3 Transducer Ph...

Page 31: ...fingers If the noise stays the same it is normal suspension noise and the driver is good Suspension noise will not be heard with program mate rial 3 Transducer Phase Test 3 1 Momentarily apply a DC voltage of 10V positive applied to the positive terminal of the test cable and GND connected to the GND terminal The bass module test cable is described in the appendix of this trouble shooting guide 3 ...

Page 32: ...e S PDIF cable to the Audio Outputs Digital jack on the back of the CD player Connect the other end of the S PDIF cable to the DATA IN jack on the PS1 Power Stand s input panel This jack is located in the middle of the panel It s an RCA jack with a white center Connect the PS1 Power Stand s AC line cord to AC mains Turn on the PS1 Wait for the power LED to light steady green Turn on the CD player ...

Page 33: ...sed with the Bass Amp3 OUT jack The load on this jack automatically sensed in order to properly tailor the EQ and output level for the connection of one or two bass modules It does this by sensing the resistive value across terminals 2 and 2 The bass modules have a 10k ohm resistor across these terminals When only one bass module is connected the PS1 sees the 10k resistance and sets the EQ and out...

Page 34: ...nel 1 and 2 insert jacks on the PS1 Power Stand When you plug it into the channel 1 or channel 2 insert jack you will be able to separate the sections of the electronics Refer to the PS1 Power Stand block diagram on page 3 The RETURN dual banana jack will give you the output of the circuitry up to the output of the 2 channel digital volume control The SEND dual banana jack will allow you to input ...

Page 35: ...ector Molex part number 39 01 2041 4 Molex crimp on pins for above connector Molex part number 39 00 0041 M 1 dual banana jack 12 feet of 16 or 18AWG twisted pair wire Cut the 12 foot length of twisted pair wire in half Strip all of the wires back about 1 4 inch Crimp the molex pins onto the wires The positive side of the twisted pair wires will go into pins 2 and 4 of the Molex connector The nega...

Page 36: ...ions A17 A7 Row Address Inputs To provide memory addresses Row addresses define a page for a Write cycle A6 A0 Column Address Inputs Column Addresses are toggled to load page data DQ7 DQ0 Data Input output To output data during Read cycles and receive input data during Write cycles Data is internally latched during a Write cycle The outputs are in tri state when OE or CE is high CE Chip Enable To ...

Page 37: ... B2 B1 B0 OE VCC PIN DESCRIPTION PIN NUMBER SYMBOL FUNCTION 1 DIR Direction 2 3 4 5 6 7 8 9 A0 to A7 Data inputs outputs 10 GND Ground 0 V 18 17 16 15 14 13 12 11 B0 to B7 Data inputs outputs 19 OE Output enable input active LOW 20 VCC Positive supply voltage 74LV245 Octal Bus Transciever PIN DESCRIPTION PIN NUMBER SYMBOL NAME AND FUNCTION 1 4 9 12 1A 4A Data inputs 2 5 10 13 1B 4B Data inputs 3 6...

Page 38: ... 48 MULTIPROCESSOR INTERFACE DUAL PORTED SRAM EXTERNAL PORT DATA BUS MUX 32 24 24 PM ADDRESS BUS DM ADDRESS BUS PM DATA BUS DM DATA BUS BUS CONNECT PX DATA REGISTER FILE 16 40 BIT BARREL SHIFTER ALU MULTIPLIER 32 48 40 CORE PROCESSOR DMA CONTROLLER PROGRAM SEQUENCER DAG2 8 4 24 SDRAM INTERFACE I 2 S 2 Rx 2Tx 2 Rx 2Tx I 2 S SPORT 0 DAG1 8 4 32 DATA DATA DATA ADDR ADDR ADDR Functional Block Diagram ...

Page 39: ...er Pin Assignments for SOIC and DIP Top View CD4093BC Quad Nand Gate C E B 2 3 1 5 4 6 nc C A CNY17G 2 Optocoupler CS4392 KZ Digital to Analog Converter DAC A1 A2 A3 6k 6k Sense 8 9 10 14 11 6 4 3 12 5 6k 6k VIN Ð VIN RG 1 VO2 VO1 V VÐ INA163 G 1 6000 RG 3k 3k VO Ref VO2 NC GS2 V Ref VO Sense VO1 NC GS1 VIN VIN V NC SO 14 NC No Internal Connection 14 13 12 11 10 9 8 1 2 3 4 5 6 7 INA163 Low Noise ...

Page 40: ...NVERSION 8 7 GND VEE 16 VCC 13 14 15 12 1 5 2 4 A7 A6 A5 A4 A3 A2 A1 A0 CHANNEL IN OUT TG TRUTH TABLE INPUT STATES ÒONÓ CHANNELS ENABLE S2 S1 S0 L L L L A0 L L L H A1 L L H L A2 L L H H A3 L H L L A4 L H L H A5 L H H L A6 L H H H A7 H X X X None X Don t Care TOP VIEW 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 A4 A6 A A7 A5 E GND VEE VCC A1 A0 A3 S0 S1 S2 A2 CHANNEL IN OUT CHANNEL IN OUT CHANNEL IN OUT...

Page 41: ...le by software Port 1 pin can also by used as alternative function T0 T1CK T1 BUZ RxD TxD D 37 32 T0 T1CK T1 BUZ RxD TxD P2 0 P2 7 I O Bit programmable I O port for Schmitt trigger input or push pull output Pull up resistors are assignable by software Port 2 pins can also be used as external interrupt D 13 20 INT0 INT7 P3 0 P3 7 I O Bit programmable I O port for Schmitt trigger input or push pull ...

Page 42: ...9459F 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 VSS L OUT NC L IN L LD1 L LD2 L A GND NC CS1 NC GND CK VDD R OUT NC R IN R LD1 R LD2 R A GND NC CS2 NC STB DATA L ch R ch TC9459F Volume Control IC ...

Page 43: ...DIX TO 92 TO 226 Pin 1 Reference 2 Anode 3 Cathode 1 2 3 TL431CLP TO 92 BLOCK DIAGRAM Note 1 Toggle flip flop used only in 1844 and 1845 UC2842 PWM Controller Pinout Diagram UC2842 PWM Controller Block Diagram ...

Page 44: ...44 APPENDIX CS5361 AD Converter Pinout and Table ...

Page 45: ...45 APPENDIX CS8406 Digital Audio Interface Transmitter ...

Page 46: ...46 APPENDIX CS8416 Digital Audio Interface Receiver ...

Page 47: ...47 APPENDIX TDA8929T Digital Amplifier Controller ...

Page 48: ...48 APPENDIX TDA8927J Digital Power Amplifier ...

Page 49: ... 2004 Bose Corporation Reference Number 264018 TG Rev 00 Troubleshooting Guide Personalized Amplification SystemTM Troubleshooting Guide ...

Page 50: ...SPECIFICATIONS AND FEATURES SUBJECT TO CHANGE WITHOUT NOTICE Bose Corporation The Mountain Framingham Massachusetts USA 01701 P N 264018 TG Rev 00 10 2004 P http serviceops bose com ...

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