14
LD485S-MP
Figure 3-2. Printed Circuit Board Layout.
J1
P2
NOTE:
DEF
AUL
T JUMPER
AND SWITCH SETTINGS SHOWN
PWR
RD
TD
CD
RTS
TST
LLB
DLB
TRANSMIT
CLOCK
SELECT
S6
O
N
O
F
F
4
3
2
1
W1
W3
RXB
RXA
TXB
TXA
TB1
P1
O F F
O N
S7
1
2
3
4
2
1
BAUD
RATE
SETTINGS
O
N
O
F
F
8
7
6
5
4
3
2
1
S5
S4
O
N
O
F
F
4
3
2
1
50ms
W2
11ms
0ms RTS/CTS
160ms
E
D
C
B
A
Constant Carrier
SWITCH MODE-JUMPER IN ONE OF
FIVE RTS/CTS DELAY POSITIONS
