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CHAPTER 9: Theory of Operation & Board Layout
9.1 Theory of Operation
The heart of the 488 Controller is a 6809 microprocessor [U101] supported by 8K bytes of firmware EPROM
[U102 (2764)] and 32K bytes of static RAM [U103 (58256)]. A Versatile Interface Adapter [U104 (65B22)]
is used to generate real-time interrupts for the firmware operating system.
The front-panel annunciators are also driven by U104 through an inverter [U113 (74LS04)]. The IEEE
488 bus interface is accomplished by a TMS9914A [U106] controller with drivers U107 and U108. The
serial interface is provided by the UART [6551 (U105)]. If RS-232 levels are chosen, they are provided
by the RS-232 transceiver (U209). If RS-422 levels are selected, the differential driver [26LS30 (U207)]
and receiver [26LS33 (U208)] are used.
The internal DIP switches [SWl, SW2, and SW3] are read via 74HCT244 tri-state buffers [U201, U202, and
U203]. Power is supplied by an external unregulated 9-volt wallmount supply. Regulation to the required
+5 volts is provided by U206 [7805].
Decoding of the microprocessor address space is accomplished with a Programmable Logic Array [U110
(16L8)]. The Memory space allocation is:
Address
Device
Part Number
Function
$0000-$7FFF
U103
58258
Static RAM
$A000-$A007
U106
9914A
IEEE Controller
$A800-$A807
U105
6551
UART
$B000-$B00F
U104
65B22
VIA
$B800
U201
74HCT244
SW1 (S201)
$B801
U202
74HCT244
SW2 (S202)
$B802
U203
74HCT244
SW3 (S203)
$E000-$FFFF
U102
2764
Programmed EPROM
9. Theory of Operation & Board Layout