BitFlow KBN-CL4-2.51-SP, Hardware Reference Manual

Page: 34 / 208

Preliminary
The Control Tables (CTABs) The Karbon
KBN-2-14 BitFlow, Inc. Version F.0
Figure 2-5 Horizontal Control
The Horizontal Control Table is made up of the following blocks:
HCOUNT - a synchronous counter that can be incremented, loaded and reset.
The clock that drives HCOUNT is a free running clock, PCLK/8, i.e., the pixel
clock divided by eight. HCOUNT is 15 bits wide and is connected to the
address input of the HCTAB.
The 15 bit HCOUNT with the PCLK/8 can generate functions up to 256K PCLKs
long, on boundaries of 8 PCLKs.
The ACPL is 17 bit, and that can generate an HAW of up to 128K PCLKs.
Logic for generating INC_H - the increment control signal to the HCOUNT.
Logic for generating LOAD_H - the load control signal to the HCOUNT. When
LOAD_H is asserted, HCOUNT is loaded with the value of 2000h.
Logic for generating RESET_H - the reset control signal to the HCOUNT. When
RESET_H is asserted, HCOUNT is reset to 0.
HCTAB - a static memory (SRAM) that outputs eight HCTAB control signals. The
address of this SRAM is driven by HCOUNT.
Logic for generating CLOCK_H - the clock to the HCOUNT. This is a frequency
divider. CLOCK_H is PCLK, the pixel clock divided by eight.
Note: If RESET_H and LOAD_H are asserted simultaneously, RESET_H overrides.
As the HCOUNT increments, it scans the address of the HCTAB in ascending order.
The output of the HCTAB depends on the data that has been written in the HCTAB by
the host. If the HCOUNT is free running, it will cyclically scan all the HCTAB’s
addresses. Any arbitrary cyclic waveform can be implemented by programming the
HCTAB with the adequate data.
15
1:8
INCREMENT
LOGIC
LOAD
LOGIC
RESET
LOGIC
RESET_H
LOAD_H
INC_H
ADDRESS
HCOUNT (COUNTER)
HCTAB (SRAM)
HCOUNT
CLOCK_H
HSTART
HRESET
ENHLOAD
Reserved
GPH0
GPH1
GPH2
GPH3
PCLK