P4M800 Pro-M7 BIOS SETUP
16
DRAM Clock/Drive Control
To control the DRAM Clock, highlight the “ Press Enter” next to the “ DRAM Clock”
label and press the enter key. The submenu will appear, providing you the following
options:
Figure 4.1: DRAM Clock/Drive Control
DRAM Clock
This item determines DRAM clock following 100MHz, 133MHz or By SPD.
The Choices:
B y SPD
(de fault), 100MHz, 133MHz, 166 MHz, 200 MHz,
266 MHz.
DRAM Timing
This item determines DRAM clock/ timing follow SPD or not.
The Choices: Auto B y SPD
(default), Manual, Turbo, Ultra.
SDRAM CAS Latency
When DRAM is installed, the number of clock cycles of CAS latency depends on
the DRAM timing.
The Choices:
2.5/4
(default), 1.5/2, 2/3, 3/5.
B ank Interleave
This item allows you to enable or disable the bank interleave feature.
The Choices: Disabled
(default), 2 Bank, 4 Bank, 8 Bank.
