Chapter 2
BIOS Setup
2-14
DRAM Timing
This item determines DRAM clock/ timing follow SPD or not.
The Choices: By SPD
(default), Manual.
DRAM CAS Latency
When DRAM is installed, the number of clock cycles of CAS latency
depends on the DRAM timing.
The Choices
:
2.5
(default), 2.
Bank Interleave
This item allows you to enable or disable the bank interleave feature.
The Choices: Disabled
(default), 2 bank, 4 bank.
Precharge to Active (Trp)
This items allows you to specify the delay from precharge command to
activate command.
The Choices
: 2T,
3T
(default).
Active to Precharge (Trcd)
This items allows you to specify the minimum bank active time.
The Choices
:
6T
(default), 5T.
Active to CMD (Trcd)
Use this item to specify the delay from the activation of a bank to the
time that a read or write command is accepted.
The Choices
: 2T,
3T
(default).
DRAM Burst Length
The Choices: 4
(default), 8.
DRAM Queue Depth
This item permits to place the depths of the memory. The deeper the
depth is, the better is this function.
The Choices: 4 level
(default), 2 level, 3 level.
DRAM Command Rate
This item controls clock cycle that must occur between the last valid
write operation and the next command.
The Choices:
1T Command,
2T Command
(default).
Summary of Contents for M7VIG Pro-D
Page 79: ...04 19 2002 ...
